Activities
From NANOxCOMP H2020 Project
(Difference between revisions)
(→Invited Talks) |
(→Presentations of Published Papers) |
||
(16 intermediate revisions by one user not shown) | |||
Line 1: | Line 1: | ||
==Presentations of Published Papers== | ==Presentations of Published Papers== | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title / type''': | ||
+ | | width="550"| Noise-induced Performance Enhancement of Variability-aware Memristor Networks / Presentation | ||
+ | |- valign="top" | ||
+ | | width="1" | '''presenter(s) - attendant(s)''': | ||
+ | | Vasileios Ntinas (DUTH) and Georigos Sirakoulis (DUTH) | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019. | ||
+ | |- valign="top" | ||
+ | | '''people reached''': | ||
+ | |Over 200 attendees, mostly researchers, both from academia and industry. | ||
+ | |||
+ | |} | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]] | ||
+ | </span> | ||
+ | <br> [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title / type''': | ||
+ | | width="550"| Analog Neural Network based on Memristor Crossbar Arrays / Presentation | ||
+ | |- valign="top" | ||
+ | | width="1" | '''presenter(s) - attendant(s)''': | ||
+ | | Hacer Yildiz (ITU) and Dogus Gungordu (ITU) | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019. | ||
+ | |- valign="top" | ||
+ | | '''people reached''': | ||
+ | |Over 300 attendees, mostly researchers, both from academia and industry. | ||
+ | |||
+ | |} | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]] | ||
+ | </span> | ||
+ | <br> [[Media:Yildiz_Crossbar_Analog_Neural_Network.pptx | Slides]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title / type''': | ||
+ | | width="550"| Testability of Switching Lattices in the Cellular Fault Model / Presentation | ||
+ | |- valign="top" | ||
+ | | width="1" | '''presenter(s) - attendant(s)''': | ||
+ | | width="550"| Luca Frontini (UMIL) – Anna Bernasconi and Valentina Ciriani (UMIL) | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019. | ||
+ | |- valign="top" | ||
+ | | '''people reached''': | ||
+ | |Over 200 attendees, mostly researchers, both from academia and industry. | ||
+ | |} | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]] | ||
+ | </span> | ||
+ | <br> [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title / type''': | ||
+ | | width="550"| Fault Mitigation of Switching Lattices under the Stuck-At Model / Presentation | ||
+ | |- valign="top" | ||
+ | | width="1" | '''presenter(s) - attendant(s)''': | ||
+ | | Lorena Anghel (INPG) | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019. | ||
+ | |- valign="top" | ||
+ | | '''people reached''': | ||
+ | |Over 100 attendees, mostly researchers, both from academia and industry. | ||
+ | |||
+ | |} | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title / type''': | ||
+ | | width="550"| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices / Presentation | ||
+ | |- valign="top" | ||
+ | | width="1" | '''presenter(s) - attendant(s)''': | ||
+ | | Levent Aksoy (ITU), Serzat Safaltin (ITU), Mustafa Altun (ITU), and Valentina Ciriani (UMIL) | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019. | ||
+ | |- valign="top" | ||
+ | | '''people reached''': | ||
+ | |Over 1600 attendees, mostly researchers, both from academia and industry. | ||
+ | |||
+ | |} | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title / type''': | ||
+ | | width="550"| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling / Presentation | ||
+ | |- valign="top" | ||
+ | | width="1" | '''presenter(s) - attendant(s)''': | ||
+ | | Serzat Safaltin (ITU), Mustafa Altun (ITU), Valentina Ciriani (UMIL), and Levent Aksoy (ITU) | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019. | ||
+ | |- valign="top" | ||
+ | | '''people reached''': | ||
+ | |Over 1600 attendees, mostly researchers, both from academia and industry. | ||
+ | |||
+ | |} | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title / type''': | ||
+ | | width="550"| Testability of Switching Lattices in the Stuck at Fault Model / Presentation | ||
+ | |- valign="top" | ||
+ | | width="1" | '''presenter(s) - attendant(s)''': | ||
+ | | width="550"| Luca Frontini (UMIL) and Valentina Ciriani (UMIL) | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018. | ||
+ | |- valign="top" | ||
+ | | '''people reached''': | ||
+ | |Over 400 attendees, mostly researchers, both from academia and industry. | ||
+ | |} | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]</span> | ||
+ | <br> [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title / type''': | ||
+ | | width="550"| Integrated Synthesis Methodology for Crossbar Arrays / Presentation | ||
+ | |- valign="top" | ||
+ | | width="1" | '''presenter(s) - attendant(s)''': | ||
+ | | Ioana Vatajelu (INPG) and Lorena Anghel (INPG) | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018. | ||
+ | |- valign="top" | ||
+ | | '''people reached''': | ||
+ | |Over 300 attendees, mostly researchers, both from academia and industry. | ||
+ | |||
+ | |} | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title / type''': | ||
+ | | width="550"| Logic Synthesis and Defect Tolerance for Memristive Crossbar Array / Presentation | ||
+ | |- valign="top" | ||
+ | | width="1" | '''presenter(s) - attendant(s)''': | ||
+ | | Mustafa Altun (ITU) and Onur Tunali (ITU) | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018. | ||
+ | |- valign="top" | ||
+ | | '''people reached''': | ||
+ | |Over 1000 attendees, mostly researchers, both from academia and industry. | ||
+ | |||
+ | |} | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
Line 257: | Line 484: | ||
==Invited Talks == | ==Invited Talks == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title / type''': | ||
+ | | width="550"| Computing with Nano-Crossbar Arrays / Keynote Talk | ||
+ | |- valign="top" | ||
+ | |'''presenter(s)''': | ||
+ | | width="550"| Mustafa Altun (ITU) | ||
+ | |- valign="top" | ||
+ | |'''presented at''': | ||
+ | | width="550"| [http://www.iaria.org/conferences2019/CENICS19.html The Twelfth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS'19)], Nice, France, 27-31 October 2019. | ||
+ | |- valign="top" | ||
+ | |'''people reached''': | ||
+ | |Over 100 attendees mostly from academia in the conference. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/8d/Altun_CENICS-2019.pptx]] | ||
+ | </span> | ||
+ | <br> [[Media:Altun_CENICS-2019.pptx | Slides]] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
Line 424: | Line 674: | ||
==Major Meetings of Project Personnel== | ==Major Meetings of Project Personnel== | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''subject''': | ||
+ | | width="550"| Annual Meeting of Project Beneficiaries | ||
+ | |- valign="top" | ||
+ | | '''attendants''': | ||
+ | | width="550"| Mustafa Altun (ITU) and Valentina Ciriani (UMIL). | ||
+ | |- valign="top" | ||
+ | | '''place''': | ||
+ | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 28 March 2019. | ||
+ | |- valign="top" | ||
+ | | '''people reached''': | ||
+ | |Private. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" |
Latest revision as of 17:24, 9 December 2019
Contents |
[edit] Presentations of Published Papers
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
[edit] Demonstrations and Exhibitions
|
|
[edit] Invited Talks
|
|
|
|
|
|
|
[edit] Online Showcasing
|
[edit] Magazine/Bulletin Columns
|
[edit] Major Meetings of Project Personnel
|
|
|
|
|
|