Publications and Presentations

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== Papers on Emerging Crossbar Memories ==
 
== Papers on Emerging Crossbar Memories ==
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| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
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| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
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| width="624" | [https://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], accepted for publication, 2019.
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[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]
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Revision as of 17:45, 11 May 2019

All materials are subject to copyrights.

Contents

Comprehensive Project Papers

title: Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
appeared in: Microprocessors and Microsystems, Vol. 54, pp. 14–25, 2017.

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Paper

title: Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance
authors: Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
presented at: Design, Automation, and Test in Europe (DATE), Lausanne, Switzerland, 2017.

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Slides

title: Synthesis and Performance Optimization of a Switching Nano-crossbar Computer
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016.

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Paper

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Slides

Papers on Logic Synthesis

title: Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches
authors: Ceylan Morgul and Mustafa Altun
accepted in: Integration, the VLSI Journal, DOI:10.1016/j.vlsi.2018.08.002, 2018.

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Paper

title: Composition of Switching Lattices for Regular and for Decomposed Functions
authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
appeared in: Microprocessors and Microsystems, Vol. 60, pp. 207–218, 2018.

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Paper

title: Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods
authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
appeared in: Microprocessors and Microsystems, Vol. 56, pp. 193–202, 2018.

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Paper

title: Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis
authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
presented at: Euromicro Conference on Digital System Design (DSD), Vienna, Austria 2017.

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Paper

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Slides

title: Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions
authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
presented at: International Conference on Very Large Scale Integration (VLSI-SoC), Tallinn, Estonia, 2016

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Paper

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Slides

title: Logic Synthesis for Switching Lattices by Decomposition with P-Circuits
authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016.

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Paper

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Slides

title: Synthesis and Optimization of Switching Nanoarrays
authors: Ceylan Morgul and Mustafa Altun
appeared in: Low-Dimensional and Nanostructured Materials and Devices, Springer International Publishing, pp. 635–660, 2016.
presented at: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Belgrade, Serbia, 2015.

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Slides

Papers on Performance Modeling and Optimization

title: Testability of Switching Lattices in the Stuck at Fault Model
authors: Anna Bernasconi, Valentina Ciriani, and Luca Frontini
presented at: International Conference on Very Large Scale Integration (VLSI-SoC), Verona, Italy 2018.

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Paper

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Poster

title: Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation
authors: Onur Tunali, Ceylan Morgul, and Mustafa Altun
accepted in: IEEE Micro, Vol. 38, Issue 5, pp. 22–31, 2018.

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Paper

title: A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays
authors: Furkan Peker and Mustafa Altun
accepted in: IEEE Transactions on Multi-Scale Computing Systems, DOI:10.1109/TMSCS.2018.2829518, 2018.

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Paper

title: Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
accepted at: Design, Automation and Test in Europe (DATE), Dresden, Germany, 2018.

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Paper

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Slides

title: Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions
authors: Onur Tunali and Mustafa Altun
accepted at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Batumi, Georgia, 2017.

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Paper

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Slides

title: A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
accepted in: IEEE Transactions on Emerging Topics in Computing, DOI: 10.1109/TETC.2017.2755458, 2017.

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Paper

title: A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
accepted in: ACM Computing Surveys, Vol. 50, No. 6, Article 79, 2017.

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Paper

title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, Issue 5, pp. 747–760, 2017.

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Paper

title: Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays
authors: Ceylan Morgul, Furkan Peker, and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016.

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Poster

Papers on Synthesis Methodology

title: Integrated Synthesis Methodology for Crossbar Arrays
authors: Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
presented at: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Athens, Greece, 2018.

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Slides

Papers on Emerging Crossbar Memories

title: Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs
authors: Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
appeared in: Microelectronics Journal, accepted for publication, 2019.

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Paper

title: Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers
authors: Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
presented at: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Taormina, Italy, 2017.

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Slides

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