Publications and Presentations

From NANOxCOMP H2020 Project
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<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
 
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
 
== Comprehensive Project Papers==
 
== Comprehensive Project Papers==
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]</span>
 +
<br>
 +
[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx Slides]
 +
|}
 +
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
  
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== Papers on Logic Synthesis ==
 
== Papers on Logic Synthesis ==
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Levent Aksoy and Mustafa Altun
 +
|- valign="top"
 +
| '''accepted&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Levent Aksoy and Mustafa Altun
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
 +
|}
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
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| Ceylan Morgul and Mustafa Altun
 
| Ceylan Morgul and Mustafa Altun
 
|- valign="top"
 
|- valign="top"
−
| '''accepted&nbsp;in''':
+
| '''appeared&nbsp;in''':
−
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], DOI:10.1016/j.vlsi.2018.08.002, 2018.
+
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60&ndash;70, 2019.
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
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|}
 
|}
  
−
== Papers on Performance Modeling and Optimization ==
+
== Papers on Fault Tolerance, Performance Modeling and Optimization ==
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez,  and Montserrat Nafria
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]</span>
 +
<br>
 +
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]
 +
</span>
 +
<br> [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
 +
|- valign="top
 +
| '''authors''':
 +
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
 +
|- valign="top"
 +
| '''presented at''':
 +
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering  (ELECO)], Bursa, Turkey, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]</span>
 +
<br>
 +
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf  | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]
 +
</span>
 +
<br> [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]
 +
 
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]
 +
</span>
 +
<br> [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
 +
|}
 +
 
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation  of Switching Lattices under the Stuck-At-Fault Model]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu
 +
 
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]
 +
</span>
 +
<br> [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
 +
|}
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
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|- valign=top
 
|- valign=top
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
−
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018
+
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
 
|}
 
|}
  
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<span class="plainlinks">
 
<span class="plainlinks">
  
−
[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_POSTER.pdf]]
+
[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]
 
</span>
 
</span>
 
<br> [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
 
<br> [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
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|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
−
| Onur Tunali, Ceylan Morgul, and [[Mustafa Altun]]
+
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
 
|- valign="top"
 
|- valign="top"
−
| '''accepted&nbsp;in''':
+
| '''appeared&nbsp;in''':
 
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22&ndash;31, 2018.
 
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22&ndash;31, 2018.
 
|}
 
|}
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| Furkan Peker and Mustafa Altun
 
| Furkan Peker and Mustafa Altun
 
|- valign="top"
 
|- valign="top"
−
| '''accepted&nbsp;in''':
+
| '''appeared&nbsp;in''':
−
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], DOI:10.1109/TMSCS.2018.2829518, 2018.
+
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
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| Onur Tunali and Mustafa Altun
 
| Onur Tunali and Mustafa Altun
 
|- valign="top"
 
|- valign="top"
−
| '''accepted&nbsp;at''':
+
| '''presented&nbsp;at''':
 
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
 
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
 
|}
 
|}
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| Onur Tunali and Mustafa Altun
 
| Onur Tunali and Mustafa Altun
 
|- valign="top"
 
|- valign="top"
−
| '''accepted&nbsp;at''':
+
| '''presented&nbsp;at''':
 
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
 
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
 
|}
 
|}
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| Onur Tunali and Mustafa Altun
 
| Onur Tunali and Mustafa Altun
 
|- valign="top"
 
|- valign="top"
−
| '''accepted&nbsp;in''':
+
| '''appeared&nbsp;in''':
 
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6,  Article 79, 2017.  
 
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6,  Article 79, 2017.  
 
|}
 
|}
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== Papers on Synthesis Methodology ==
 
== Papers on Synthesis Methodology ==
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Lorena Anghel, Valentina Ciriani, Ioana Vatajelu, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
 +
|- valign=top
 +
| '''appeared&nbsp;in''':
 +
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=7729 IEEE Transactions on Nanotechnology], early access, 2020.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf]]</span>
 +
<br>
 +
[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Paper]]
 +
 +
|}
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
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== Papers on Emerging Crossbar Memories ==
 
== Papers on Emerging Crossbar Memories ==
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
 +
|- valign=top
 +
| '''appeared&nbsp;in''':
 +
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]</span>
 +
<br>
 +
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]
 +
 +
|}
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
Line 529: Line 755:
 
</span>
 
</span>
 
<br> [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
 
<br> [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
 +
|}
 +
 +
== Papers on Technology Development ==
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | CMOS Implementation of Switching Lattices]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Ismail Cevik, Levent Aksoy, and Mustafa Altun
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx Slides]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
 
|}
 
|}

Latest revision as of 11:15, 3 December 2020

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Contents

[edit] Comprehensive Project Papers

title: Nano-Crossbar based Computing: Lessons Learned and Future Directions
authors: Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
presented at: Design, Automation, and Test in Europe (DATE), Grenoble, France, 2020.

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title: Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
appeared in: Microprocessors and Microsystems, Vol. 54, pp. 14–25, 2017.

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title: Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance
authors: Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
presented at: Design, Automation, and Test in Europe (DATE), Lausanne, Switzerland, 2017.

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title: Synthesis and Performance Optimization of a Switching Nano-crossbar Computer
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016.

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[edit] Papers on Logic Synthesis

title: Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices
authors: Levent Aksoy and Mustafa Altun
accepted in: IEEE Transactions on Computers, 2019.

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title: A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices
authors: Levent Aksoy and Mustafa Altun
presented at: Design, Automation and Test in Europe (DATE), Florence, Italy, 2019.

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title: Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches
authors: Ceylan Morgul and Mustafa Altun
appeared in: Integration, the VLSI Journal, Vol. 64, pp. 60–70, 2019.

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title: Composition of Switching Lattices for Regular and for Decomposed Functions
authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
appeared in: Microprocessors and Microsystems, Vol. 60, pp. 207–218, 2018.

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title: Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods
authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
appeared in: Microprocessors and Microsystems, Vol. 56, pp. 193–202, 2018.

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title: Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis
authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
presented at: Euromicro Conference on Digital System Design (DSD), Vienna, Austria 2017.

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title: Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions
authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
presented at: International Conference on Very Large Scale Integration (VLSI-SoC), Tallinn, Estonia, 2016

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title: Logic Synthesis for Switching Lattices by Decomposition with P-Circuits
authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016.

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title: Synthesis and Optimization of Switching Nanoarrays
authors: Ceylan Morgul and Mustafa Altun
appeared in: Low-Dimensional and Nanostructured Materials and Devices, Springer International Publishing, pp. 635–660, 2016.
presented at: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Belgrade, Serbia, 2015.

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[edit] Papers on Fault Tolerance, Performance Modeling and Optimization

title: Noise-induced Performance Enhancement of Variability-aware Memristor Networks
authors: Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
presented at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Genova, Italy, 2019.

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title: Analog Neural Network based on Memristor Crossbar Arrays
authors: Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
presented at: International Conference on Electrical and Electronics Engineering (ELECO), Bursa, Turkey, 2019.

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title: Testability of Switching Lattices in the Cellular Fault Model
authors: Anna Bernasconi, Valentina Ciriani, and Luca Frontini
presented at: Euromicro Conference on Digital System Design (DSD), Chalkidiki, Greece, 2019.

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title: Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model
authors: Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu
presented at: IEEE Latin American Test Symposium (LATS), Santiago, Chile, 2019.

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title: Testability of Switching Lattices in the Stuck at Fault Model
authors: Anna Bernasconi, Valentina Ciriani, and Luca Frontini
presented at: International Conference on Very Large Scale Integration (VLSI-SoC), Verona, Italy 2018.

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Poster

title: Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation
authors: Onur Tunali, Ceylan Morgul, and Mustafa Altun
appeared in: IEEE Micro, Vol. 38, Issue 5, pp. 22–31, 2018.

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title: A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays
authors: Furkan Peker and Mustafa Altun
appeared in: IEEE Transactions on Multi-Scale Computing Systems, Vol. 4, No. 4, pp. 522–532, 2018.

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title: Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
presented at: Design, Automation and Test in Europe (DATE), Dresden, Germany, 2018.

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title: Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions
authors: Onur Tunali and Mustafa Altun
presented at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Batumi, Georgia, 2017.

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title: A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
accepted in: IEEE Transactions on Emerging Topics in Computing, DOI: 10.1109/TETC.2017.2755458, 2017.

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title: A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: ACM Computing Surveys, Vol. 50, No. 6, Article 79, 2017.

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title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, Issue 5, pp. 747–760, 2017.

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title: Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays
authors: Ceylan Morgul, Furkan Peker, and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016.

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[edit] Papers on Synthesis Methodology

title: Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance
authors: Ceylan Morgul, Luca Frontini, Onur Tunali, Lorena Anghel, Valentina Ciriani, Ioana Vatajelu, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
appeared in: IEEE Transactions on Nanotechnology, early access, 2020.

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title: Integrated Synthesis Methodology for Crossbar Arrays
authors: Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
presented at: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Athens, Greece, 2018.

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[edit] Papers on Emerging Crossbar Memories

title: Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs
authors: Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
appeared in: Microelectronics Journal, Vol. 89, pp. 30-36, 2019.

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title: Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers
authors: Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
presented at: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Taormina, Italy, 2017.

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[edit] Papers on Technology Development

title: CMOS Implementation of Switching Lattices
authors: Ismail Cevik, Levent Aksoy, and Mustafa Altun
presented at: Design, Automation, and Test in Europe (DATE), Grenoble, France, 2020.

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title: Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling
authors: Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
presented at: Design, Automation and Test in Europe (DATE), Florence, Italy, 2019.

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