Research

We aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Our objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

Logic Synthesis

We study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a diode, a FET, and a four-terminal switch. For these three types, we give array size formulations for a given Boolean function. Additionally, we focus on four-terminal switch based implementations and propose an algorithm that implements Boolean functions with optimal array sizes. Selected Publications title: Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco presented at: International Conference on Very Large Scale Integration (VLSI-SoC), Tallinn, Estonia, 2016 Paper Slides title: Synthesis and Performance Optimization of a Switching Nano-crossbar Computer authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016. Paper Slides Developed Tools title: Optimal Synthesis Tool authors: Ceylan Morgul and Mustafa Altun description: Two optimal synthesis tools Tool-1 and Tool-2 are developed in Matlab and Python, respectively. Both tools aim to synthesize a given target Boolean functions with an optimal size of four-terminal switch based arrays . Tool

Fault Tolerance

We examine reconfigurable crossbar arrays by considering randomly occurred stuck-open and stuck-closed crosspoint faults. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions Selected Publications title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays authors: Onur Tunali and Mustafa Altun accepted in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016. Paper Developed Tools title: Fault Tolerant Logic Mapping Tool authors: Onur Tunali and Mustafa Altun description: The tool is developed in Matlab. It aims to map logic funtions into fault crossbars such that each crosspoint has an independent fault probability up to 20%. Tool

Performance Modeling and Analysis

In this study, we introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. Although the proposed model is technology independent, we explicitly show its applicability for three different nanoarray technologies where each crosspoint behaves as a diode, a FET, and a four-terminal switch. In order to find related capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies. Comparison between the proposed model and a conventional simple one, which generally uses one/two capacitors for each crosspoint, demonstrates the necessity of using our model in order to accurately calculate power and delay values. The only exception where both models give approximately same results is the presence of considerably low valued resistive connections between switches. However, we show that this is a rare case for nano-crossbar technologies. Selected Publications title: Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays authors: Ceylan Morgul, Furkan Peker, and Mustafa Altun presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016. Paper Poster