Research

We aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Our objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

Logic Synthesis

We study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a diode, a FET, and a four-terminal switch. For these three types, we give array size formulations for a given Boolean function. Additionally, we focus on four-terminal switch based implementations and propose an algorithm that implements Boolean functions with optimal array sizes. Selected Publications title: Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco presented at: International Conference on Very Large Scale Integration (VLSI-SoC), Tallinn, Estonia, 2016 Paper Slides title: Synthesis and Performance Optimization of a Switching Nano-crossbar Computer authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016. Paper Slides Developed Tools title: Optimal Synthesis Tool authors: Ceylan Morgul and Mustafa Altun description: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016. Paper

Fault Tolerance

We examine reconfigurable crossbar arrays by considering randomly occurred stuck-open and stuck-closed crosspoint faults. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions Synthesis and Optimization We propose a fast synthesis algorithm that implements any given reversible Boolean function with quantum gates. Instead of an exhaustive search on every given function, our algorithm creates a library of essential functions and performs sorting. As an example, to implement 4 bit circuits we only use 120 essential functions out of all 20922789888000 functions. We also perform optimization for both reversible and quantum circuit costs by considering adjacent gate pairs. Selected Publications title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays authors: Onur Tunali and Mustafa Altun accepted in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016. Paper Developed Tools title: Optimal Synthesis Tool authors: Ceylan Morgul and Mustafa Altun description: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016. Paper

Performance Modeling and Analysis

Accurate Arithmetic Implementations We propose a method to overcome the main drawback in stochastic computing, low accuracy or related long computing times. Our method manipulates stochastic bit streams with the aid of feedback mechanisms. We implement error-free arithmetic multiplier and adder circuits by considering performance parameters area, delay, and accuracy. Selected Publications title: Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays authors: Ceylan Morgul, Furkan Peker, and Mustafa Altun presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016. Paper Poster Funding Projects title: Implementation of Accurate Stochastic Circuit Blocks and their Applications for Printed/Flexible Electronic Systems agency & program: TUBITAK Scientific and Technological Research Projects Funding Program (1001) budget: 265.400 TL duration: 2017-2020