Research

We aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Our objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

Logic Synthesis

We study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a diode, a FET, and a four-terminal switch. For these three types, we give array size formulations for a given Boolean function. Additionally, we focus on four-terminal switch based implementations and propose an algorithm that implements Boolean functions with optimal array sizes. Selected Publications title: Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco presented at: International Conference on Very Large Scale Integration (VLSI-SoC), Tallinn, Estonia, 2016 Paper Slides title: Synthesis and Performance Optimization of a Switching Nano-crossbar Computer authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016. Paper Slides Developed Tools title: Optimal Synthesis Tool authors: Ceylan Morgul and Mustafa Altun description: Two optimal synthesis tools Tool-1 and Tool-2 are developed in Matlab and Python, respectively. Both tools aim to synthesize a given target Boolean functions with an optimal size of four-terminal switch based arrays . Tool

Fault Tolerance

We examine reconfigurable crossbar arrays by considering randomly occurred stuck-open and stuck-closed crosspoint faults. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions Since density feature of crossbar architectures is the main attracting point, we perform a detailed yield analysis by considering both uniform and non-uniform defect distributions. We formalize an approximate successful mapping probability metric for uniform distributions and determine area overheads. Selected Publications title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays authors: Onur Tunali and Mustafa Altun appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, Issue 5, pp. 747–760, 2017. Paper title: Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions authors: Onur Tunali and Mustafa Altun accepted at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Batumi, Georgia, 2017. Paper Slides Developed Tools title: Fault Tolerant Logic Mapping Tool authors: Onur Tunali and Mustafa Altun description: The tool is developed in Matlab. It aims to map logic funtions into fault crossbars such that each crosspoint has an independent fault probability up to 20%. Tool title: Yield Analysis Tool authors: Onur Tunali and Mustafa Altun description: The tool is developed in Matlab. This tool calculates the required crossbar size in advance according to a given logic function and a defect rate. Tool accepts two parameters, logic function file and defect rate as inputs and returns the size of crossbar. Tool

Performance Modeling and Analysis

We introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. In order to find capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies. Selected Publications title: Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays authors: Ceylan Morgul, Furkan Peker, and Mustafa Altun presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016. Paper Poster

Technology Development and Performance Optimization

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures. Computing with crossbar arrays is achieved by its crosspoints behaving as switches, either two-terminal or four-terminal. Depending on the technology used, a two-terminal switch behaves as a diode, a resistive/memristive switch, or a field effect transistor (FET). On the other hand, a four-terminal switch has a unique behavior. While there have been many different technologies proposed for two-terminal switch based arrays, technology development for four-terminal switch based arrays, called switching lattices, has recently started. For both two-terminal and four-terminal switch based arrays, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. We also aim to develeop CMOS-compatible technologies for crossbar arrays, specifically for switching lattices. Technology Development Although a four-terminal switch based array offers a significant area advantage, in terms of the number of switches, compared to the ones having two-terminal switches, its realization at the technology level needs further justifications and raises a number of questions about its feasibility. We answer these questions. First, by using three dimensional technology computer-aided design (TCAD) simulations, we show that four-terminal switches can be directly implemented with the CMOS technology. For this purpose, we try different semiconductor gate materials in different formations of geometric shapes. Then, by fitting the TCAD simulation data to the standard CMOS current-voltage equations, we develop a Spice model of a four-terminal switch. Finally, we successfully perform Spice circuit simulations on four-terminal switches with different sizes. Performance Optimization We study crossbar arrys including the memristive ones. We propose a defect-tolerant logic synthesis algorithms by considering area, delay, and power costs of the arrays. Selected Publications title: Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling authors: Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun presented at: Design, Automation and Test in Europe (DATE), Florence, Italy, 2019. Paper Slides title: Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation authors: Onur Tunali and Mustafa Altun appeared in: IEEE Micro, Vol. 38, Issue 5, pp. 22–31, 2018. presented at: Design, Automation and Test in Europe (DATE), Dresden, Germany, 2018. Paper Slides title: Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori appeared in: Microprocessors and Microsystems, Vol. 54, pp. 14–25, 2017. presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016. Paper Slides