Research

Our research aims to develop novel ways of computing, circuit design, and reliability for electronic circuits and systems. Our research mainly targets emerging technologies and new computing paradigms.

Computing with Nano-Crossbar Arrays

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Synthesis We study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a diode, a FET, and a four-terminal switch. For these three types, we give array size formulations for a given Boolean function. Additionally, we focus on four-terminal switch based implementations and propose an algorithm that implements Boolean functions with optimal array sizes. Fault Tolerance We examine reconfigurable crossbar arrays by considering randomly occurred stuck-open and stuck-closed crosspoint faults. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions Selected Publications title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays authors: Onur Tunali and Mustafa Altun accepted in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016. presented at: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Boston, USA, 2015. Paper Slides title: Synthesis and Performance Optimization of a Switching Nano-crossbar Computer authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori accepted at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016. Paper Slides title: Logic Synthesis for Switching Lattices authors: Mustafa Altun and Marc Riedel appeared in: IEEE Transactions on Computers, Vol. 61, Issue 11, pp. 1588–1600, 2012. presented at: Design Automation Conference (DAC), Anaheim, USA, 2010. Paper Slides Funding Projects title: Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer agency & program: European Union/European Commission H2020 MCSA Research and Innovation Staff Exchange Program (RISE) budget: 724.500 EURO duration: 2015-2019 title: Synthesis and Reliability Analysis of Nano Switching Arrays agency & program: TUBITAK Career Program (3501) budget: 189.509 TL duration: 2014-2017

Reversible Circuit Design

Unlike conventional logic gates, reversible logic gates do not have “don’t-care” conditions. It means that an error occurring in any node of a reversible circuit is always seen at the output that gives a unique opportunity for error detecting/correcting. Motivated by this, we implement error tolerant reversible circuit blocks by exploiting parity preserving logic and Hamming codes. We aim to design, fabricate, and test a fault-aware 8-bit reversible microprocessor for applications requiring high accuracy and reliability including aerospace, military, and medical applications. Synthesis and Optimization We propose a fast synthesis algorithm that implements any given reversible Boolean function with quantum gates. Instead of an exhaustive search on every given function, our algorithm creates a library of essential functions and performs sorting. As an example, to implement 4 bit circuits we only use 120 essential functions out of all 20922789888000 functions. We also perform optimization for both reversible and quantum circuit costs by considering adjacent gate pairs. Selected Publications title: Fast Synthesis of Reversible Circuits using a Sorting Algorithm and Optimization authors: Omercan Susam and Mustafa Altun accepted in: Journal of Multiple-Valued Logic and Soft Computing, 2016. presented at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Marseille, France, 2014. Paper Slides Funding Projects title: Implementation of a Fault-Aware 8-Bit Reversible Microprocessor agency & program: TUBITAK Short Term R&D Funding Program (1002) budget: 30.000 TL duration: 2016-2017 title: Quantum Circuit Design and Computation agency & program: Istanbul Technical University Research Support Program (ITU-BAP) duration: 2014-2015, completed

Stochastic Circuit Design

Accurate Arithmetic Implementations We propose a method to overcome the main drawback in stochastic computing, low accuracy or related long computing times. Our method manipulates stochastic bit streams with the aid of feedback mechanisms. We implement error-free arithmetic multiplier and adder circuits by considering performance parameters area, delay, and accuracy. Selected Publications title: Accurate Synthesis of Arithmetic Operations with Stochastic Logic authors: Ensar Vahapoglu and Mustafa Altun accepted at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016. Paper Poster Reliability of Electronic Products The rapid developments in electronics, especially in the last decade, have elevated the importance of electronics reliability. Conventionally used accelerated reliability tests have lost their significance; time consuming and expensive feature of these tests is against the demands of today's very rapid electronic product cycles. In this study, we propose less costly, yet accurate, reliability prediction techniques using field return data, new accelerated test methodologies, and physics of failure based simulations. We cooperate with one of the Europe’s largest household appliance companies Arçelik A.Ş.. Reliability Analysis and Prediction with Field Data We propose an accurate reliability prediction model for high-volume electronic products throughout their warranty periods by using field return data. Our model is constructed on a Weibull-exponential hazard rate scheme by using the proposed change point detection method based on backward and forward data analysis. Our prediction model can make a 36-month (full warranty) reliability prediction of an electronic board with using its field data as short as 3 months. Degradation Processes in Varistors We investigate different degradation mechanisms of ZnO varistors. We propose a model showing how the varistor voltage Vv changes by time for different stress levels. For this purpose, accelerated degradation tests are applied for different AC current levels; then voltage values are measured. Different from the common practice in the literature that considers a degradation with only decreasing Vv values, we demonstrate either an increasing or a decreasing trend in the Vv parameter. Calibrated Accelerated Life Testing Dramatic decrease in failure rates for electronic products makes conventional accelerated life tests (ALT) extremely time consuming and costly. Recently proposed calibrated accelerated life tests (CALT) aim to use fewer samples than those used in ALT. We thoroughly compare ALT and CALT by considering the effects of failure rate, acceleration factor, and stress level on the required test time. Selected Publications title: A Change-Point based Reliability Prediction Model using Field Return Data authors: Mustafa Altun and Vehbi Comert accepted in: Reliability Engineering and System Safety, 2016. presented at: Reliability and Maintainability Symposium (RAMS), Palm Harbor, USA, 2015. Paper Slides title: Effects of ZnO Varistor Degradation on the Overvoltage Protection Mechanism of Electronic Boards authors: Hadi Yadavari, Burak Sal, Mustafa Altun, Ertunc Erturk, and Baris Ocak presented at: European Safety and Reliability Conference (ESREL), Zurich, Switzerland, 2015. Paper Slides title: Extensive Investigation of Calibrated Accelerated Life Testing (CALT) in Comparison with Classical Accelerated Life Testing (ALT) authors: Burak Sal and Mustafa Altun presented at: European Safety and Reliability Conference (ESREL), Zurich, Switzerland, 2015. Paper Slides Funding Projects title: An Accurate Reliability Methodology for Appliance Electronic Cards agency & program: TUBITAK University-Industry Collaboration Grant Program (1505) budget: 211.800 TL duration: 2013-2015, completed title: Gate Oxide Breakdown Failure Mechanism of CMOS Transistors agency & program: TUBITAK Industry Oriented Senior Project Support Program (2241/A) duration: 2013-2014, completed Analog Circuit Design Positive Feedback The conventional wisdom is that analog circuits should not include positive feedback loops. As controversial as it seems, we have successfully used positive feedback for impedance improvement in a current amplifier. With adding few transistors we have achieved very low input resistance values. Additionally, we have proposed a new fully-differential current amplifier and tested it in a filter application. Selected Publications title: Design of a Fully Differential Current Mode Operational Amplifier with its Filter Applications authors: Mustafa Altun and Hakan Kuntman appeared in: AEU International Journal of Electronics and Communications, Vol. 62, Issue 3, pp. 39–44, 2008. presented at: ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa, Italy, 2007. Paper Slides Discrete Mathematics Self Duality Problem The problem of testing whether a monotone Boolean function in irredundant disjuntive normal form (IDNF) is self-dual is one of few problems in circuit/time complexity whose precise tractability status is unknown. We have focused on this famous problem. We have shown that monotone self-dual Boolean functions in IDNF do not have more variables than disjuncts. We have proposed an algorithm to test whether a monotone Boolean function in IDNF with n variables and n disjuncts is self-dual. The algorithm runs in O(n^3) time. Selected Publications title: A Study on Monotone Self-dual Boolean Functions authors: Mustafa Altun and Marc Riedel appeared  in: Acta Mathematicae Applicatae Sinica - English Series, Vol. 32, Issue 3, 2016. Paper Slides