EHB 322E

Revision as of 16:50, 14 April 2014

Apr. 9th The second homework has been posted that is due 21/04/2014 (before the lecture).
Apr. 7th To see your grades click here.
Mar. 4th The first homework has been posted that is due 17/03/2014 (before the lecture).
Feb. 11th As a simulation tool, Spice is required for homeworks. Among different Spice-based programs, LTspice is a good and free choice; you can download it by clicking here.
Feb. 3rd The class is given in the room 4102 (first floor), EEF.

EHB 322E: Digital Electronic Circuits, CRN: 25176, Mondays 13:30-16:30, Room: 4102 (EEF), Spring 2014.

Instructor	Mustafa Altun Email: altunmus@itu.edu.tr Tel: 02122856635 Office hours: 15:00 – 16:30 on Tuesdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant	Salih Vehbi Cömert Email: vehbicomert@gmail.com Room: 3007 EEF
Grading	Quizzes: 10% 2 pop-up quizzes (5% each) - no prior announcement of quiz dates and times Homeworks: 10% 3 homeworks (3.3% each) Midterm Exams: 40% 2 midterms (20% each) during the lecture time that will on 24/3/2014 and 28/4/2014. Final Exam: 40%
Reference Books	Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (2002). Digital integrated circuits. Englewood Cliffs: Prentice hall. Uyemura, J. P. (2002). CMOS logic circuit design. Springer. Kang, S. M., & Leblebici, Y. (2003). Cmos Digital Integrated Circuits, 3/E. Tata McGraw-Hill Education.
Policies	Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date. Quizzes and exams are in closed-notes and closed-books format. To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least 25 (out of 100).

Date	Topic
Week 1, 10/2/2014	Introduction
Week 2, 17/2/2014	Devices for digital circuits and inverters
Week 3, 24/2/2014	NMOS/CMOS inverters & their static and dynamic behaviors
Weeks 4, 3/3/2014	Optimization of multiple-stage inverters and buffers
Weeks 5, 10/3/2014	Static logic gates
Week 6, 17/3/2014	Complex logic gates and their delays
Weeks 7, 24/3/2014	MIDTERM I
Week 8, 31/3/2014	Pass transistor logic
Week 9, 7/4/2014	Pass transistor logic & Dynamic logic gates
Weeks 10, 14/4/2014	Dynamic logic gates
Week 11, 21/4/2014	Flip-flops
Week 12, 28/4/2014	MIDTERM II
Weeks 13, 5/5/2014	Synchronization of digital circuits
Weeks 14, 12/5/2014	Semiconductor memories and gate arrays

@@ Line 80: / Line 80: @@
 |  Week  8, 31/3/2014      || Pass transistor logic
 |-
-|  Week  9, 7/4/2014     || Dynamic logic gates
+|  Week  9, 7/4/2014     || Pass transistor logic & Dynamic logic gates
 |-
 |  Weeks 10, 14/4/2014 ||  Dynamic logic gates