EHB 322E

Revision as of 22:41, 16 March 2017

Mar. 16th Midterm-1 will be held in rooms 5302 and 5202 between 15:30 - 17:30 on March 20th.
Feb. 20th The first homework has been posted that is due 06/03/2016 (before the lecture).
Feb. 6th The class is given in the room 5302 (third floor), EEF.
Feb. 3rd As a simulation tool, Spice is required for homeworks. Among different Spice-based programs, LTspice is a good and free choice; you can download it by clicking here.

EHB 322E: Digital Electronic Circuits, CRN: 21161, Mondays 13:30-16:30, Room: 5302 (EEF), Spring 2017.

Instructor	Mustafa Altun Email: altunmus@itu.edu.tr Tel: 02122856635 Office hours: 15:00 – 16:30 on Tuesdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant	Furkan Peker Email: furkan.peker061@gmail.com Room: 3207 EEF
Grading	Quizzes: 10% 2 pop-up quizzes (5% each) - no prior announcement of quiz dates and times Homeworks: 10% 3 homeworks (3.3% each) Midterm Exams: 40% 2 midterms (20% each) during the lecture time that will on 20/3/2017 and 24/4/2017. Final Exam: 40%
Reference Books	Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (20XX). Digital integrated circuits. Englewood Cliffs: Prentice hall. Uyemura, J. P. (20XX). CMOS logic circuit design. Springer. Kang, S. M., & Leblebici, Y. (20XX). Cmos Digital Integrated Circuits. McGraw-Hill Education.
Policies	Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date. Quizzes and exams are in closed-notes and closed-books format. To be eligible of taking the final or the resit exam, your midterm average should be at least 25 (out of 100).

Date	Topic
Week 1, 6/2/2017	Introduction
Week 2, 13/2/2017	Switching theory & devices for digital circuits and inverters
Week 3, 20/2/2017	NMOS/CMOS inverters & their static and dynamic behaviors
Weeks 4, 27/2/2017	Optimization of multiple-stage inverters and buffers
Weeks 5, 6/3/2017	Static logic gates and area-delay-power performance analysis
Week 6, 13/3/2017	Complex logic gates and their delays
Weeks 7, 20/3/2017	MIDTERM I
Week 8, 27/3/2017	HOLIDAY, no class
Week 9, 3/4/2017	Pass transistor logic with Shannon's expansion and performance analysis
Weeks 10, 10/4/2017	Dynamic logic gates, synchronization, and performance analysis
Week 11, 17/4/2017	Static and dynamic memory elements: D, SR, and JK flip-flops
Week 12, 24/4/2017	MIDTERM II
Weeks 13, 1/5/2017	HOLIDAY, no class
Weeks 14, 8/5/2017	Synchronization and timing analysis of digital circuits having logic and memory elements
Weeks 15, 15/5/2017	Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories

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 == Announcements ==
+* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Mar. 16th</span> Midterm-1 will be held in rooms '''5302''' and '''5202''' between '''15:30 - 17:30''' on March 20th.
 * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Feb. 20th</span> [[Media:ehb322e-2017-spring-hw-01.pdf | '''The first homework''']] has been posted that is due 06/03/2016 (before the lecture).
 * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Feb. 6th</span>  The class is given in the room '''5302''' (third floor), EEF.