BLG 231E
From NANOxCOMP H2020 Project
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== Announcements == | == Announcements == | ||
− | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> | + | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Aug. 26th</span> The class is given in the room '''5204''' (second floor), EEF. |
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== Syllabus == | == Syllabus == | ||
− | <div style="font-size: 120%;"> '''BLG 231E: Digital Circuits''', CRN: | + | <div style="font-size: 120%;"> '''BLG 231E: Digital Circuits''', CRN: 10647, Fridays 09:30-12:30, Room: 5204 (EEF), Fall 2016. </div> |
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* Email: altunmus@itu.edu.tr | * Email: altunmus@itu.edu.tr | ||
* Tel: 02122856635 | * Tel: 02122856635 | ||
− | * Office hours: 15:00 – 16:30 on | + | * Office hours: 15:00 – 16:30 on Tuesdays in Room:3005, EEF (or stop by my office any time) |
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| <div style="font-size: 120%;"> '''Teaching Assistant'''</div> | | <div style="font-size: 120%;"> '''Teaching Assistant'''</div> | ||
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* Email: furkan.peker061@gmail.com | * Email: furkan.peker061@gmail.com | ||
* Room: 3207 EEF | * Room: 3207 EEF | ||
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+ | Ensar Vahapoğlu | ||
+ | * Email: ensarvahapoglu@gmail.com | ||
+ | * Room: 3007 EEF | ||
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| <div style="font-size: 120%;"> '''Grading'''</div> | | <div style="font-size: 120%;"> '''Grading'''</div> |
Revision as of 09:43, 26 August 2016
Contents |
Announcements
- Aug. 26th The class is given in the room 5204 (second floor), EEF.
Syllabus
BLG 231E: Digital Circuits, CRN: 10647, Fridays 09:30-12:30, Room: 5204 (EEF), Fall 2016.
Instructor
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Teaching Assistant
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Furkan Peker
Ensar Vahapoğlu
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Grading
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Textbook
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Reference Books
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Policies
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Weekly Course Plan
Date
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Topic
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Week 1, 15/9/2015 | Introduction |
Week 2, 22/9/2015 | HOLIDAY, no class |
Week 3, 29/9/2015 | Digital logic fundamentals: gates, combinational circuits, Boolean expressions |
Weeks 4, 6/10/2015 | Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares" |
Weeks 5, 13/10/2015 | Logic minimization: Karnaugh maps, Quine-McCluskey method |
Week 6, 20/10/2015 | Quine-McCluskey method, binary decision diagrams, hazards |
Weeks 7, 27/10/2015 | MIDTERM I |
Week 8, 3/11/2015 | Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.) |
Week 9, 10/11/2015 | Combinational circuit design: implementing Boolean and arithmetic operations |
Weeks 10, 17/11/2015 | Performance analysis of combinational circuits |
Week 11, 24/11/2015 | Sequential circuits: latches & flip-flops |
Week 12, 1/12/2015 | MIDTERM II |
Weeks 13, 8/12/2015 | Sequential circuit design: state graphs and tables, modules |
Weeks 14, 15/12/2015 | Sequential circuit design: modules, state machines |
Weeks 15, 22/12/2015 | Sequential circuit design: modules, state machines |
Course Materials
Homeworks & Solutions | Exams |
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Homework 1 & Solutions | Midterm 1 |
Homework 2 & Solutions | Midterm 2 |
Homework 3 & Solutions | Final |