EHB 322E

Revision as of 22:26, 3 June 2016

June 3rd To see your final grades click here.
May 23th Final exam will be held in rooms 2106 and 5102 between 15:00 - 17:00 on May 25st.
May 9th The third homework has been posted that is due 18/05/2016 before 16:30 (submit to my office #3005 or our lab #3007).
Apr. 24th Midterm-2 will be held in rooms 5201 and Z4 between 15:30 - 17:30 on April 25st.
Apr. 4th The second homework has been posted that is due 18/04/2016 (before the lecture).
Mar. 20th Midterm-1 will be held in rooms 5107 and 5201 between 13:30 - 15:30 on March 21st.
Feb. 22nd The first homework has been posted that is due 07/03/2016 (before the lecture).
Feb. 5th As a simulation tool, Spice is required for homeworks. Among different Spice-based programs, LTspice is a good and free choice; you can download it by clicking here.
Feb. 5th The class is given in the room 5201 (second floor), EEF.

EHB 322E: Digital Electronic Circuits, CRN: 20767, Mondays 13:30-16:30, Room: 5201 (EEF), Spring 2016.

Instructor	Mustafa Altun Email: altunmus@itu.edu.tr Tel: 02122856635 Office hours: 15:00 – 16:30 on Tuesdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant(s)	Furkan Peker Email: furkan.peker061@gmail.com Room: 3207 EEF Ensar Vahapoğlu Email: ensarvahapoglu@gmail.com Room: 3007 EEF
Grading	Quizzes: 10% 2 pop-up quizzes (5% each) - no prior announcement of quiz dates and times Homeworks: 10% 3 homeworks (3.3% each) Midterm Exams: 40% 2 midterms (20% each) during the lecture time that will on 21/3/2016 and 25/4/2016. Final Exam: 40%
Reference Books	Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (2002). Digital integrated circuits. Englewood Cliffs: Prentice hall. Uyemura, J. P. (2002). CMOS logic circuit design. Springer. Kang, S. M., & Leblebici, Y. (2003). Cmos Digital Integrated Circuits, 3/E. Tata McGraw-Hill Education.
Policies	Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date. Quizzes and exams are in closed-notes and closed-books format. To be eligible of taking the final or the resit exam, your midterm average should be at least 25 (out of 100).

Date	Topic
Week 1, 8/2/2016	Introduction
Week 2, 15/2/2016	Devices for digital circuits and inverters
Week 3, 22/2/2016	NMOS/CMOS inverters & their static and dynamic behaviors
Weeks 4, 29/2/2016	Optimization of multiple-stage inverters and buffers
Weeks 5, 7/3/2016	Static logic gates
Week 6, 14/3/2016	Complex logic gates and their delays
Weeks 7, 21/3/2016	MIDTERM I
Week 8, 28/3/2016	Pass transistor logic
Week 9, 4/4/2016	Pass transistor logic & Dynamic logic gates
Weeks 10, 11/4/2016	Dynamic logic gates
Week 11, 18/4/2016	Flip-flops
Week 12, 25/4/2016	MIDTERM II
Weeks 13, 2/5/2016	Synchronization of digital circuits
Weeks 14, 9/5/2016	Semiconductor memories and gate arrays

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 == Announcements ==
-* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> May 27th</span> To see your grades [[Media:ehb322e-2016-spring-grades.pdf | ''' click here''']].
+* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> June 3rd</span> To see your final grades [[Media:ehb322e-2016-spring-final-grades.pdf | ''' click here''']].
 * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> May 23th</span> Final exam will be held in rooms '''2106''' and '''5102''' between '''15:00 - 17:00''' on May 25st.
 * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> May 9th</span> [[Media:ehb322e-2016-spring-hw-03.pdf | '''The third homework''']] has been posted that is due 18/05/2016 before 16:30 (submit to my office #3005 or our lab #3007).