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From NANOxCOMP H2020 Project
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* We publicly introduce our project in [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event]. | * We publicly introduce our project in [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event]. | ||
| − | + | <!-- * Our two papers in the area of ''fault tolerance for nano-crossbar arrays'' are accepted in journals [http://csur.acm.org/ CSUR] and [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 TETC] having impact factors of 6,8 and 3,8. This endorses our leading expertise in this area. --> | |
| − | * Our two papers in the area of ''fault tolerance for nano-crossbar arrays'' are accepted in journals [http://csur.acm.org/ CSUR] and [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 TETC] having impact factors of 6,8 and 3,8. This endorses our leading expertise in this area. | + | |
* We present our work "''Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis''" in [http://dsd-seaa2017.ocg.at/dsd2017 DSD 2017]. | * We present our work "''Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis''" in [http://dsd-seaa2017.ocg.at/dsd2017 DSD 2017]. | ||
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* We present our work "''Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2017]. | * We present our work "''Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2017]. | ||
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| − | * Our paper is accepted in a leading journal in design automation [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE TCAD]. | + | * Our paper is accepted in a leading journal in design automation [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE TCAD]. --> |
* We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016]. | * We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016]. | ||
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* We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry. | * We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry. | ||
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| − | * We publish a book chapter "''Computing with Emerging Nanotechnologies''" in a book [http://link.springer.com/book/10.1007/978-3-319-25340-4 "Low-Dimensional and Nanostructured Materials and Devices"]. | + | * We publish a book chapter "''Computing with Emerging Nanotechnologies''" in a book [http://link.springer.com/book/10.1007/978-3-319-25340-4 "Low-Dimensional and Nanostructured Materials and Devices"]. --> |
[[Image:nanoxcomp_logo.png|center|none|300px|link=]] | [[Image:nanoxcomp_logo.png|center|none|300px|link=]] | ||
Revision as of 12:59, 17 November 2019
Welcome to the NANOxCOMP Project | |
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Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Project objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.
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This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.
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