EHB 322E

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|  Week  1, 8/2/2016       || Introduction  
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|  Week  1, 6/2/2017       || Introduction  
 
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|  Week  2, 15/2/2016     || Switching theory & devices for digital circuits and inverters
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|  Week  2, 13/2/2017     || Switching theory & devices for digital circuits and inverters
 
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|  Week  3, 22/2/2016       || NMOS/CMOS inverters & their static and dynamic behaviors
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|  Week  3, 20/2/2017       || NMOS/CMOS inverters & their static and dynamic behaviors
 
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|  Weeks 4, 29/2/2016 || Optimization of multiple-stage inverters and buffers  
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|  Weeks 4, 27/2/2017 || Optimization of multiple-stage inverters and buffers  
 
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|  Weeks 5, 7/3/2016   || Static logic gates and area-delay-power performance analysis
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|  Weeks 5, 6/3/2017   || Static logic gates and area-delay-power performance analysis
 
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|  Week 6, 14/3/2016       || Complex logic gates and their delays
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|  Week 6, 13/3/2017       || Complex logic gates and their delays
 
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|  Weeks 7, 21/3/2016   || MIDTERM I  
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|  Weeks 7, 20/3/2017   || MIDTERM I  
 
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|  Week  8, 28/3/2016     || Pass transistor logic with Shannon's expansion and performance analysis
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|  Week  8, 27/3/2017     || Pass transistor logic with Shannon's expansion and performance analysis
 
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|  Week  9, 4/4/2016   ||  Dynamic logic gates, synchronization, and performance analysis
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|  Week  9, 3/4/2017   ||  Dynamic logic gates, synchronization, and performance analysis
 
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|  Weeks 10, 11/4/2016 ||  Problems and solutions in dynamic logic
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|  Weeks 10, 10/4/2017 ||  Problems and solutions in dynamic logic
 
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|  Week  11, 18/4/2016     || Static and dynamic memory elements: D, SR, and JK flip-flops  
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|  Week  11, 17/4/2017     || Static and dynamic memory elements: D, SR, and JK flip-flops  
 
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|  Week  12, 25/4/2016     || MIDTERM II  
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|  Week  12, 24/4/2017     || MIDTERM II  
 
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|  Weeks 13, 2/5/2016 || Synchronization and timing analysis of digital circuits having logic and memory elements
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|  Weeks 13, 1/5/2017 || HOLIDAY, no class
 
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|  Weeks 14, 9/5/2016 || Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories
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|  Weeks 14, 8/5/2017 || Synchronization and timing analysis of digital circuits having logic and memory elements
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|  Weeks 15, 15/5/2017 || Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories
 
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Revision as of 10:39, 3 February 2017

Contents

Announcements

  • Feb. 3rd As a simulation tool, Spice is required for homeworks. Among different Spice-based programs, LTspice is a good and free choice; you can download it by clicking here.
  • Feb. 3rd The class is given in the room 5306 (third floor), EEF.

Syllabus

EHB 322E: Digital Electronic Circuits, CRN: 20767, Mondays 13:30-16:30, Room: 5201 (EEF), Spring 2016.
Instructor

Mustafa Altun

  • Email: altunmus@itu.edu.tr
  • Tel: 02122856635
  • Office hours: 15:00 – 16:30 on Tuesdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant

Ensar Vahapoğlu

  • Email: ensarvahapoglu@gmail.com
  • Room: 3007 EEF
Grading
  • Quizzes: 10%
    • 2 pop-up quizzes (5% each) - no prior announcement of quiz dates and times
  • Homeworks: 10%
    • 3 homeworks (3.3% each)
  • Midterm Exams: 40%
    • 2 midterms (20% each) during the lecture time that will on 21/3/2016 and 25/4/2016.
  • Final Exam: 40%
Reference Books
  • Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (2002). Digital integrated circuits. Englewood Cliffs: Prentice hall.
  • Uyemura, J. P. (2002). CMOS logic circuit design. Springer.
  • Kang, S. M., & Leblebici, Y. (2003). Cmos Digital Integrated Circuits, 3/E. Tata McGraw-Hill Education.
Policies
  • Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date.
  • Quizzes and exams are in closed-notes and closed-books format.
  • To be eligible of taking the final or the resit exam, your midterm average should be at least 25 (out of 100).

Weekly Course Plan

Date
Topic
Week 1, 6/2/2017 Introduction
Week 2, 13/2/2017 Switching theory & devices for digital circuits and inverters
Week 3, 20/2/2017 NMOS/CMOS inverters & their static and dynamic behaviors
Weeks 4, 27/2/2017 Optimization of multiple-stage inverters and buffers
Weeks 5, 6/3/2017 Static logic gates and area-delay-power performance analysis
Week 6, 13/3/2017 Complex logic gates and their delays
Weeks 7, 20/3/2017 MIDTERM I
Week 8, 27/3/2017 Pass transistor logic with Shannon's expansion and performance analysis
Week 9, 3/4/2017 Dynamic logic gates, synchronization, and performance analysis
Weeks 10, 10/4/2017 Problems and solutions in dynamic logic
Week 11, 17/4/2017 Static and dynamic memory elements: D, SR, and JK flip-flops
Week 12, 24/4/2017 MIDTERM II
Weeks 13, 1/5/2017 HOLIDAY, no class
Weeks 14, 8/5/2017 Synchronization and timing analysis of digital circuits having logic and memory elements
Weeks 15, 15/5/2017 Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories

Course Materials

Homeworks & Solutions Quizzes & Solutions Exams
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