BLG 231E
From NANOxCOMP H2020 Project
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Revision as of 16:11, 27 October 2015
Contents |
Announcements
- Oct. 26th Midterm-1 will be held in room 2106 between 13:30 - 15:30.
- Oct. 6th The first homework has been posted that is due 20/10/2014 before 13:30.
- Sept. 12th The class is given in the room 2106 (first floor), EEF.
Syllabus
BLG 231E: Digital Circuits, CRN: 12876, Tuesdays 13:30-16:30, Room: 2106 (EEF), Fall 2015.
Instructor
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Teaching Assistant
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Furkan Peker
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Grading
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Textbook
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Reference Books
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Policies
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Weekly Course Plan
Date
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Topic
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Week 1, 15/9/2015 | Introduction |
Week 2, 22/9/2015 | HOLIDAY, no class |
Week 3, 29/9/2015 | Digital logic fundamentals: gates, combinational circuits, Boolean expressions |
Weeks 4, 6/10/2015 | Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares" |
Weeks 5, 13/10/2015 | Logic minimization: Karnaugh maps, Quine-McCluskey method |
Week 6, 20/10/2015 | Quine-McCluskey method, binary decision diagrams, hazards |
Weeks 7, 27/10/2015 | MIDTERM I |
Week 8, 3/11/2015 | Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.) |
Week 9, 10/11/2015 | Combinational circuit design: implementing Boolean and arithmetic operations |
Weeks 10, 17/11/2015 | Performance analysis of combinational circuits |
Week 11, 24/11/2015 | Sequential circuits: latches & flip-flops |
Week 12, 1/12/2015 | MIDTERM II |
Weeks 13, 8/12/2015 | Sequential circuit design: state graphs and tables, modules |
Weeks 14, 15/12/2015 | Sequential circuit design: modules, state machines |
Weeks 15, 22/12/2015 | Sequential circuit design: modules, state machines |
Course Materials
Homeworks & Solutions | Exams |
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Homework 1 | Midterm 1 |