ELE 523E

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Revision as of 12:48, 14 September 2015

Contents

Announcements

  • Sept. 12th The class is given in the room Z2 (ground floor), EEF.

Overview

As current CMOS based technologies are approaching their anticipated limits, emerging nanotechnologies are expected to replace their role in electronic circuits. This course overviews nanoelectronic circuits in a comparison with those of conventional CMOS-based. Deterministic and probobalistic emerging computing models are investigated. Regarding the interdisciplinary nature of emerging technologies, this course is appropriate for graduate students in different majors including electronics engineering, control engineering, computer science, applied physics, and mathematics. No prior course is required; only basic (college-level) knowledge in circuit design and mathematics is assumed. Topics that are covered include:

  • Devices in computational nanoelectronics (in comparison with CMOS) including nano arrays, switches, and transistors.
  • Introduction of emerging computing models in circuit level.
  • Analysis and synthesis of deterministic and probabilistic models.
  • Performance of the computing models regarding area, power, speed, and accuracy.
  • Uncertainty and defects: defect tolerance techniques for permanent and transient errors.

Syllabus

ELE 523E: Computational Nanoelectronics, CRN: 14647, Mondays 13:30-16:30, Room: Z2 (Ground Floor-EEF), Fall 2015.
Instructor

Mustafa Altun

  • Email: altunmus@itu.edu.tr
  • Tel: 02122856635
  • Office hours: 13:30 – 15:00 on Thursdays in Room:3005, EEF (or stop by my office any time)
Grading
  • Homework: 15%
    • 3 homeworks (5% each)
  • Midterm Exam: 25%
    • The midterm is during the lecture time on 23/11/2015.
  • Presentation: 20%
    • Presentations are made individually or in groups depending on class size.
    • Presentation topics will be posted.
  • Final Project: 40%
Reference Books
  • Zomaya, Y. (2006). Handbook of Nature-Inspired and Innovative Computing: Integrating Classical Models with Emerging Technologies, Springer.
  • Yanushkevich, S., Shmerko, V., Lyshevski, S. (2005). Logic Design of NanoICs, CRC Press.
  • Adamatzky, A., Bull, L., Costello, B. L., Stepney, S., Teuscher, C. (2007). Unconventional Computing, Luniver Press.
  • Stanisavljević, M., Schmid, M, Leblebici, Y. (2010). Reliability of Nanoscale Circuits and Systems: Methodologies and Circuit Architectures, Springer.
  • Sasao, T. (1999). Switching Theory for Logic Synthesis, Springer.
Policies
  • Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date.
  • Collaboration is permitted and encouraged for homeworks, but each collaborator should turn in his/her own answers.
  • The midterm is in closed-notes and closed-books format.
  • Collaboration is not permitted for the final project.

Weekly Course Plan

Date
Topic
Week 1, 14/9/2015 Introduction
Week 2, 21/9/2015 Introduction
Week 3, 28/9/2015 Overview of emerging nanoscale devices and switches
Weeks 4, 5/10/2015 Reversible quantum computing
Weeks 5, 12/10/2015 Synthesis and optimization of reversible circuits
Week 6, 19/10/2015 Computing with switching nano arrays
Weeks 7, 26/10/2015 Stochastic/Probabilistic computing
Week 8, 2/11/2015 Performance optimization for stochastic computing
Week 9, 9/11/2015 Defects and reliability in nanoelectronics
Weeks 10, 16/11/2015 Defect tolerance analysis and techniques
Week 11, 23/11/2015 MIDTERM
Week 12, 30/11/2015 Overview of the midterm, the presentation schedule, and the final project
Weeks 13, 7/12/2015 Student presentations
Weeks 14, 14/12/2015 Student presentations
Weeks 15, 21/12/2015 Student presentations

Course Materials

Lecture Slides Lecture Slides Lecture Slides Homeworks Presentations & Exams & Projects
W1: Introduction
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