BLG 231E
From NANOxCOMP H2020 Project
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− | + | * Homeworks: '''15%''' | |
− | + | ** 3 homeworks (5% each) | |
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− | * Homeworks: ''' | + | |
− | ** 3 homeworks ( | + | |
* Midterm Exams: '''40%''' | * Midterm Exams: '''40%''' | ||
− | ** 2 midterms ( | + | ** 2 midterms (22.5% each) during the lecture time that will on 24/3/2014 and 28/4/2014. |
* Final Exam: '''40%''' | * Final Exam: '''40%''' |
Revision as of 19:12, 7 September 2014
Contents |
Announcements
- Sept. 7th The class is given in the room 2104 (first floor), EEF.
Syllabus
BLG 231E: Digital Circuits, CRN: 11043, Tuesdays 13:30-16:30, Room: 2104 (EEF), Fall 2014.
Instructor
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Teaching Assistant
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Salih Vehbi Cömert
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Grading
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Reference Books
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Policies
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Weekly Course Plan
Date
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Topic
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Week 1, 10/2/2014 | Introduction |
Week 2, 17/2/2014 | Devices for digital circuits and inverters |
Week 3, 24/2/2014 | NMOS/CMOS inverters & their static and dynamic behaviors |
Weeks 4, 3/3/2014 | Optimization of multiple-stage inverters and buffers |
Weeks 5, 10/3/2014 | Static logic gates |
Week 6, 17/3/2014 | Complex logic gates and their delays |
Weeks 7, 24/3/2014 | MIDTERM I |
Week 8, 31/3/2014 | Pass transistor logic |
Week 9, 7/4/2014 | Pass transistor logic & Dynamic logic gates |
Weeks 10, 14/4/2014 | Dynamic logic gates |
Week 11, 21/4/2014 | Flip-flops |
Week 12, 28/4/2014 | MIDTERM II |
Weeks 13, 5/5/2014 | Synchronization of digital circuits |
Weeks 14, 12/5/2014 | Semiconductor memories and gate arrays |
Course Materials
Homeworks & Solutions | Quizzes | Exams |
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Homework 1 & Solutions | Quiz 1 | Midterm 1 |
Homework 2 & Solutions | Quiz 2 | Midterm 2 |
Homework 3 |