Research
| Line 210: | Line 210: | ||
|} | |} | ||
| + | {| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;" | ||
| + | |||
| + | | | ||
| + | {| | ||
| + | |- valign=top | ||
| + | | width="100" |'''title''': | ||
| + | | width="524"|[[Media:Tunali_Altun_Yield_Analysis_Tool.zip | Yield Analysis Tool]] | ||
| + | |- valign="top" | ||
| + | | '''authors''': | ||
| + | | Onur Tunali and Mustafa Altun | ||
| + | |- valign="top" | ||
| + | | '''description''': | ||
| + | | width="524"| The tool is developed in Matlab. This tool calculates the required crossbar size in advance according to a given logic function and a defect rate. Using a crossbar with determined size, a valid physical implementation of the logic function with a reconfigurable nano-crossbar array can be achieved. Tool accepts two parameters, logic function file and defect rate as inputs and returns the size of crossbar. | ||
| + | |} | ||
| + | | align=center width="70" | | ||
| + | <span class="plainlinks"> | ||
| + | [[File:ZIP.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/16/Tunali_Altun_Yield_Analysis_Tool.zip]]</span> | ||
| + | <br> | ||
| + | [[Media:Tunali_Altun_Yield_Analysis_Tool.zip | Tool]] | ||
| + | |} | ||
| + | |||
|} | |} | ||
Revision as of 12:23, 27 November 2017
We aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Our objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.
Logic Synthesis | |||||||||||||||||||||||||||||||||
|
We study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a diode, a FET, and a four-terminal switch. For these three types, we give array size formulations for a given Boolean function. Additionally, we focus on four-terminal switch based implementations and propose an algorithm that implements Boolean functions with optimal array sizes. 
| |||||||||||||||||||||||||||||||||
Fault Tolerance | |||||||||||||||||||||||||||||||
|
We examine reconfigurable crossbar arrays by considering randomly occurred stuck-open and stuck-closed crosspoint faults. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions 
| |||||||||||||||||||||||||||||||
Performance Modeling and Analysis | |||||||||||||
|
We introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. In order to find capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies. 
| |||||||||||||
