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From NANOxCOMP H2020 Project
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* We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016]. | * We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016]. | ||
| − | * We present our project and our work on ''logic synthesis of switching | + | * We present our project and our work on ''logic synthesis of switching nanoarrays'' in [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 DSD 2016]. |
* We give an invited talk "''EU H2020 Success Story''" in [http://msca-association.teamwork.fr/en/programme H2020 MSCA 2016 Istanbul Training & Info Event]. | * We give an invited talk "''EU H2020 Success Story''" in [http://msca-association.teamwork.fr/en/programme H2020 MSCA 2016 Istanbul Training & Info Event]. | ||
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* We give an invited talk "''Circuit Design and Optimization of Nano-Crossbar Arrays''" in [http://www.nanotr12.org/ NanoTR-12]. | * We give an invited talk "''Circuit Design and Optimization of Nano-Crossbar Arrays''" in [http://www.nanotr12.org/ NanoTR-12]. | ||
| − | * We give a plenary talk "''Implementation of a Switching Nano-Crossbar Computer''" in [http://www.wseas.org/cms.action?id=11327 | + | * We give a plenary talk "''Implementation of a Switching Nano-Crossbar Computer''" in [http://www.wseas.org/cms.action?id=11327 ACS 2016]. |
* We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry. | * We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry. | ||
Revision as of 20:16, 14 April 2017
Welcome to the NANOxCOMP Project | |
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Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Project objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.
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