Research - Revision history

Altun at 15:00, 13 May 2019

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Altun at 15:00, 13 May 2019

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Altun at 14:59, 13 May 2019

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Altun at 13:10, 13 May 2019

2019-05-13T13:10:50Z

Altun at 12:57, 13 May 2019

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Altun at 12:51, 13 May 2019

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Altun at 12:47, 13 May 2019

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Altun at 12:31, 13 May 2019

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Altun at 12:21, 13 May 2019

2019-05-13T12:21:14Z

Show changes

Altun at 09:35, 27 November 2017

2017-11-27T09:35:55Z

@@ Line 587: / Line 587: @@
 performance to that of the current sensing amplifier in terms of power, speed, and bit error rate performance.
-[[Image:Crossbar-memory.png|center|none|600px|link=]]
+[[Image:Crossbar-memory.png|center|none|500px|link=]]
 <!--        YAYIN       -->

@@ Line 527: / Line 527: @@
 area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization
 algorithms for each step of the process.
 [[Image:Research-synthesis-methodology.png|center|none|800px|link=]]

@@ Line 586: / Line 586: @@
 performance to that of the current sensing amplifier in terms of power, speed, and bit error rate performance.
-[[Image:Crossbar-memory.png|center|none|800px|link=]]
+[[Image:Crossbar-memory.png|center|none|600px|link=]]
 <!--        YAYIN       -->

← Older revision		Revision as of 13:10, 13 May 2019
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	\|}		\|}

		+	\|}
		+
		+
		+	{\| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
		+	\|-
		+	\| colspan="2" style="background:#8FBC7F; text-align:center; padding:1px; border-bottom:1px #8FBC8F solid;" \|
		+	<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Crossbar Memories </h2>
		+	\|-
		+	\| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> \|
		+
		+	In this work, we investigated the sensing challenges of spin-transfer torque MRAMs structured as nano-crossbar memories. To overcome
		+	the problems of reading this type of memory, we have proposed a voltage sensing amplifier topology and compared its
		+	performance to that of the current sensing amplifier in terms of power, speed, and bit error rate performance.
		+
		+	[[Image:Crossbar-memory.png\|center\|none\|800px\|link=]]
		+
		+	<!-- YAYIN -->
		+	{\| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"
		+	\| class="MainPageBG" style="width:50%; border:0px solid #D8BFD8; vertical-align:top; color:#000;" \|
		+	{\| id="mp-left" style="width:100%; vertical-align:top;"
		+
		+	\|
		+
		+	{\| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
		+
		+	\|- valign=top
		+	\| width="696" \|'''Selected Publications'''
		+	\|}
		+	{\| style="border:1px solid #abd5f5; background:#f1f5fc;"
		+
		+	\|
		+	{\|
		+	\|- valign=top
		+	\| width="100" \|'''title''':
		+	\| width="450"\|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf \| Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
		+	\|- valign="top"
		+	\| '''authors''':
		+	\| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
		+	\|- valign="top"
		+	\| '''appeared in''':
		+	\| width="450"\| [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], accepted for publication, 2019.
		+	\|- valign="top"
		+	\| '''presented at''':
		+	\| width="450"\| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
		+	\|}
		+	\| align=center width="70" \|
		+	<span class="plainlinks">
		+	[[File:PDF.png\|65px\|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]</span>
		+	<br>
		+	[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf \| Paper]]
		+	\| align="center" width="70" \|
		+	<span class="plainlinks">
		+
		+	[[File:PPT.jpg\|60px\|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]
		+	</span>
		+	<br> [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
		+	\|}
		+
		+	\|}
		+	\| style="border:1px solid transparent;" \|
		+	<!-- PROJE -->
		+
		+	\|}
	\|}		\|}

@@ Line 513: / Line 513: @@
 |-
 | colspan="2" style="background:#8FBC8F; text-align:center; padding:1px; border-bottom:1px #8FBC9F solid;" |
-<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Reliability of Electronic Products </h2>
+<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Complete Synthesis Methodology </h2>
 |-
 | valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
-The rapid developments in electronics, especially in the last decade, have elevated the importance of electronics reliability. Conventionally used accelerated reliability tests have lost their significance; time consuming and expensive feature of these tests is against the demands of today's very rapid electronic product cycles. In this study, we propose less costly, yet accurate, reliability prediction techniques using field return data, new accelerated test methodologies, and physics of failure based simulations. We cooperate with one of the Europe’s largest household appliance companies [http://www.arcelik.com.tr/default.aspx?lang=en-US Arçelik A.Ş.].
+Due to the stochastic nature
-[[Image:Research-3.png|center|none|800px|link=]]
+[[Image:Research-synthesis-methodology.png|center|none|800px|link=]]
 <!--        YAYIN       -->
@@ Line 555: / Line 550: @@
 |- valign=top
 | width="100" |'''title''':
-| width="450"|[[Media:Altun_Comert_A_Change-Point_based_Reliability_Prediction_Model_using_Field_Return_Data.pdf| A Change-Point based Reliability Prediction Model using Field Return Data]]
+| width="450"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
 |- valign="top"
 | '''authors''':
-| [[Mustafa Altun]] and Vehbi Comert
+| width="450"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
-|- valign=top
+|- valign="top"
-| '''appeared&nbsp;in''':
-| width="450"| [http://www.journals.elsevier.com/reliability-engineering-and-system-safety Reliability Engineering and System Safety], Vol. 156, pp. 175&ndash;184, 2016.
 |- valign=top
 | '''presented&nbsp;at''':
-| width="450"| [http://rams.org/ Reliability and Maintainability Symposium (RAMS)], Palm Harbor, USA, 2015.
+| width="450"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
 |}
 | align=center width="70" |
 <span class="plainlinks">
-[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/1/16/Altun_Comert_A_Change-Point_based_Reliability_Prediction_Model_using_Field_Return_Data.pdf]]</span>
+[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]</span>
 <br>
-[[Media:Altun_Comert_A_Change-Point_based_Reliability_Prediction_Model_using_Field_Return_Data.pdf | Paper]]
+[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf | Paper]]
 | align="center" width="70" |
 <span class="plainlinks">
-[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/a/a7/Comert_Altun_Nadar_Erturk_Warranty_Forecasting_of_Electronic_Boards_using_Short-term_Field_Data.pptx]]
+[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]
 </span>
-<br> [http://www.ecc.itu.edu.tr/images/a/a7/Comert_Altun_Nadar_Erturk_Warranty_Forecasting_of_Electronic_Boards_using_Short-term_Field_Data.pptx Slides]
+<br> [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
 |}
 |}

@@ Line 505: / Line 505: @@
 <!--        PROJE      -->
 |}
 |}

@@ Line 364: / Line 364: @@
 Performance Optimization</h3>
-We study crossbar arrys including the memristive ones. We
+We study crossbar arrays including the memristive ones. We
 propose a '''defect-tolerant logic synthesis algorithms by considering area, delay, and power costs''' of the arrays.
 <!-- [[Image:Research-2.png|center|none|800px|link=]] -->

@@ Line 333: / Line 333: @@
 {| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
 |-
-| colspan="2" style="background:#8FBCCF; text-align:center; padding:1px; border-bottom:1px #8FBCCF solid;" |
+| colspan="2" style="background:#8FBC9F; text-align:center; padding:1px; border-bottom:1px #8FBCAF solid;" |
 <h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Technology Development and Performance Optimization </h2>

← Older revision		Revision as of 09:35, 27 November 2017
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	We examine reconfigurable crossbar arrays by considering randomly occurred '''stuck-open and stuck-closed crosspoint faults'''. In the presence of '''permanent''' faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of '''transient''' faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions		We examine reconfigurable crossbar arrays by considering randomly occurred '''stuck-open and stuck-closed crosspoint faults'''. In the presence of '''permanent''' faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of '''transient''' faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions
		+
		+	Since '''density''' feature of crossbar architectures is the main attracting point, we perform a detailed yield analysis by considering both uniform and non-uniform defect distributions.
		+	We formalize an approximate successful mapping probability metric for uniform distributions
		+	and determine '''area overheads'''.

	[[Image:nanoarray_fault_tolerance.png\|center\|none\|500px\|link=]]		[[Image:nanoarray_fault_tolerance.png\|center\|none\|500px\|link=]]