NANOxCOMP H2020 Project - User contributions [en]

Publications and Presentations

2020-12-03T08:15:38Z

Altun:

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]
 
[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx]]

 [http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Lorena Anghel, Valentina Ciriani, Ioana Vatajelu, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=7729 IEEE Transactions on Nanotechnology], early access, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | CMOS Implementation of Switching Lattices]]
|- valign="top"
| '''authors''':
| Ismail Cevik, Levent Aksoy, and Mustafa Altun
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf]]
 
[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2020-12-03T08:13:52Z

Altun: /* Comprehensive Project Papers */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]
 
[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx]]

 [http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Lorena Anghel, Valentina Ciriani, Ioana Vatajelu, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=7729 IEEE Transactions on Nanotechnology], early access, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==


{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2020-12-03T08:13:19Z

Altun: /* Comprehensive Project Papers */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]
 
[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Lorena Anghel, Valentina Ciriani, Ioana Vatajelu, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=7729 IEEE Transactions on Nanotechnology], early access, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==


{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2020-12-03T08:11:30Z

Altun: /* Papers on Synthesis Methodology */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==


{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Lorena Anghel, Valentina Ciriani, Ioana Vatajelu, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=7729 IEEE Transactions on Nanotechnology], early access, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==


{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2020-12-03T08:11:16Z

Altun: /* Comprehensive Project Papers */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==


{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==


{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

File:Morgul EtAl Circuit Design Steps for Nano Crossbar Arrays.pdf

2020-12-03T08:10:27Z

Altun:

Publications and Presentations

2020-12-03T08:10:00Z

Altun: /* Comprehensive Project Papers */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Lorena Anghel, Valentina Ciriani, Ioana Vatajelu, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=7729 IEEE Transactions on Nanotechnology], early access, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==


{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Main Page

2020-05-07T14:25:26Z

Altun:

__NOTOC__

{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
|-
| colspan="2" style="background:#CEDFF2; text-align:center; padding:1px; border-bottom:1px #B8C7D9 solid;" |
<h2 style="margin:.5em; margin-top:.1em; border-bottom:1px; font-weight:bold;">
Welcome to the NANOxCOMP Project</h2>
|-
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;"  |

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer.

Project objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

[[Image:Research-nanoarray-1.png|center|none|800px|link=]]

<h2 id="mp-itn-h2" style="margin:0px; width:1010px; background:#F5F5F5; font-size:5%; font-weight:bold; border:0px solid #F5F5F5; text-align:left; color:#000; padding:0em 0em;"> </h2>

|}


{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"

| class="MainPageBG" style="width:50%; border:1px solid #B8C7D9; background:#8FBCCF; vertical-align:top; color:#000;" |
{| id="mp-left" style="width:100%; vertical-align:top; background:#F5F5F5;"

| style="padding:2px;" | <h2 id="mp-tafi-h2" style="margin:3px; background:#5F9EA0; font-size:125%; font-weight:bold; border:1px solid #4682B4; text-align:left; color:#000; padding:0.2em 0.4em;">Project details</h2>

{|
|- valign=top
| width="140" |'''title''':
| width="500"|Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
|- valign="top"
| width="140" |'''acronym''':
| width="500"|NANOxCOMP
|- valign="top"
| '''principal investigator / coordinator''':
| [http://www.ecc.itu.edu.tr/index.php?title=Mustafa_Altun Mustafa Altun], [http://www.ecc.itu.edu.tr/index.php?title=Main_Page ECC Group, Istanbul Technical University]
|- valign="top"
| '''partner(s)''':
| width="500"|
* Dr. Dan Alexandrescu, [http://www.iroctech.com/ IROC Techonogies], France 
* Prof. Lorena Anghel, [http://tima.imag.fr/tima/en/index.html TIMA Lab.], France (''partnership terminated'') 
* Prof. Valentina Ciriani, [http://alos.di.unimi.it/ ALOS Lab., University of Milan], Italy. 
* Prof. Csaba A. Moritz, [http://www.umass.edu/nanofabrics/ Nanoscale Computing Fabrics Lab., University of Massachusetts], USA 
* Prof. Kaushik Roy, [http://engineering.purdue.edu/NRL/index.html Nanoelectronics Research Lab., Purdue University], USA 
* Prof. Georgios Sirakoulis, [http://www.ee.duth.gr/en/ Department of Electrical and Computer Engineering, Democritus University of Thrace], Greece (''new partner'') 
* Prof. Mircea Stan, [http://hplp.ece.virginia.edu/home High-Performance Low-Power Lab., University of Virginia], USA 
* Prof. Mehdi B. Tahoori, [http://cdnc.itec.kit.edu/index.php Dependable Nano-Computing Group, Karlsruhe Institute of Technology], Germany

|- valign="top"
| '''funding agency & program''':
| width="500"| [http://ec.europa.eu/research/mariecurieactions/about-msca/actions/rise/index_en.htm European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)] [http://www.youtube.com/watch?v=dVeJFeKYrLs&feature=youtu.be RISE Video]
|- valign="top"
| '''budget''':
| 724.500 EURO
|- valign="top"
| '''duration''':
| 2015-2019
|}

{| style="margin-left: auto; margin-right: auto; border:1px solid #abd5f5; background:#CEDFE0; padding:0.2em 0.5em;"

|- valign=top
| |'''This project'''
* gathers globally leading research groups working on nanoelectronics and EDA;
* targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories; and
* contributes to the construction of emerging computers beyond CMOS by proposing nano-crossbar based computer architectures.
[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

[[Image:nanoxcomp_partners.png|center|none|450px|link=]]

|}

{|BORDER=0>
|-
<div><center>

'''PRESENTATIONS'''
<li style="display: inline-block;">


[[File:PPT.jpg|70px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]

</center></div>
|}

|}

----

<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.

| style="border:1px solid transparent;" |


| class="MainPageBG" style="width:50%; border:1px solid #BA55D3; background:#F8F8FF; vertical-align:top;"|
{| id="mp-right" style="width:100%; vertical-align:top; background:#F8F8FF;"
| style="padding:2px;" |

<h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project by the numbers, 2015-2019 </h2>
Started in 2015, the project has been successfully completed in 2019 with many achievements including:

* 34 researchers have been seconded to project partners, performing a total of 110,93 secondment months. 17 of them are early stage researchers and 9 of them are female researchers.

* 32 peer-reviewed papers contributed by 30 project secondees or partners have been published. 12 of them are journal papers.

* 35 dissemination, outreach, and management activities have been performed.

|}

<h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project activity news </h2>

* We present our work "''Nano-Crossbar based Computing: Lessons Learned and Future Directions''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''CMOS Implementation of Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''Analog Neural Network based on Memristor Crossbar Arrays''" in [http://www.eleco.org.tr/ ELECO 2019].

* We present our work "''Noise-induced Performance Enhancement of Variability-aware Memristor Networks''" in [http://www.ieee-icecs2019.org/ ICECS 2019].

* We give a keynote talk "''Computing with Nano-crossbar Arrays''" in [http://www.iaria.org/conferences2019/CENICS19.html CENICS 2019].

* We present our work "''Testability of Switching Lattices in the Cellular Fault Model''" in [http://dsd-seaa2019.csd.auth.gr/ DSD 2019].

* A new partner Prof. Georgios Sirakoulis from Democritus University of Thrace, Greece has joined our consortium. Welcome!

* We present our work "''Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model''" in [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ LATS 2019].

* We present our work "''Testability of Switching Lattices in the Stuck at Fault Model''" in [http://vlsi-soc.di.univr.it/ VLSI-Soc 2018].

* We present our work "''Integrated Synthesis Methodology for Crossbar Arrays''" in a leading conference on nanocircuits/nanoarchitectures [http://www.nanoarch.org IEEE/ACM-NANOARCH 2018].

* We showcase our project in a [http://youtu.be/iwMSSvE1y8s YouTube video].

* We present our work "''Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2018].

* We present our work "''Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions''" in [http://icecs2017.org/ IEEE-ICECS 2017].

* We publicly introduce our project in [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event].


* We present our work "''Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis''" in [http://dsd-seaa2017.ocg.at/dsd2017 DSD 2017].

* We present our work "''Spintronic Memristor based Offset Cancellation Technique for Sense Amplifiers''" in [http://smacd2017.unisa.it/ SMACD 2017].

* We successfully have our midterm review meeting in Lausanne, Switzerland on March 2017. For the agenda [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | click here]].

* We present our work "''Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2017].


* We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016].

* We present our project and our work on ''logic synthesis of switching nanoarrays'' in [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 DSD 2016].

* We give an invited talk "''EU H2020 Success Story''" in [http://msca-association.teamwork.fr/en/programme H2020 MSCA 2016 Istanbul Training & Info Event].

* We present our work "''Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays''" in [http://www.isvlsi.org/ IEEE-ISVLSI 2016].

* We organize [http://sintesilogica.di.unimi.it/ the National Workshop on Logic Synthesis, July 2016] with introducing our project and preliminary research results.

* We give an invited talk "''Circuit Design and Optimization of Nano-Crossbar Arrays''" in [http://www.nanotr12.org/ NanoTR-12].

* We give a plenary talk "''Implementation of a Switching Nano-Crossbar Computer''" in [http://www.wseas.org/cms.action?id=11327 ACS 2016].

* We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry.


[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

<!--
----
<div style="margin-left:0.8em;">If interested, please contact [[Mustafa_Altun|Mustafa]]:
* '''email:''' altunmus@itu.edu.tr
* '''office:''' EEF 3005 (coffee guaranteed)</div> -
<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.->
|}
|}

Main Page

2020-02-24T06:18:53Z

Altun:

__NOTOC__

{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
|-
| colspan="2" style="background:#CEDFF2; text-align:center; padding:1px; border-bottom:1px #B8C7D9 solid;" |
<h2 style="margin:.5em; margin-top:.1em; border-bottom:1px; font-weight:bold;">
Welcome to the NANOxCOMP Project</h2>
|-
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;"  |

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer.

Project objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

[[Image:Research-nanoarray-1.png|center|none|800px|link=]]

<h2 id="mp-itn-h2" style="margin:0px; width:1010px; background:#F5F5F5; font-size:5%; font-weight:bold; border:0px solid #F5F5F5; text-align:left; color:#000; padding:0em 0em;"> </h2>

|}


{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"

| class="MainPageBG" style="width:50%; border:1px solid #B8C7D9; background:#8FBCCF; vertical-align:top; color:#000;" |
{| id="mp-left" style="width:100%; vertical-align:top; background:#F5F5F5;"

| style="padding:2px;" | <h2 id="mp-tafi-h2" style="margin:3px; background:#5F9EA0; font-size:125%; font-weight:bold; border:1px solid #4682B4; text-align:left; color:#000; padding:0.2em 0.4em;">Project details</h2>

{|
|- valign=top
| width="140" |'''title''':
| width="500"|Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
|- valign="top"
| width="140" |'''acronym''':
| width="500"|NANOxCOMP
|- valign="top"
| '''principal investigator / coordinator''':
| [http://www.ecc.itu.edu.tr/index.php?title=Mustafa_Altun Mustafa Altun], [http://www.ecc.itu.edu.tr/index.php?title=Main_Page ECC Group, Istanbul Technical University]
|- valign="top"
| '''partner(s)''':
| width="500"|
* Dr. Dan Alexandrescu, [http://www.iroctech.com/ IROC Techonogies], France 
* Prof. Lorena Anghel, [http://tima.imag.fr/tima/en/index.html TIMA Lab.], France (''partnership terminated'') 
* Prof. Valentina Ciriani, [http://alos.di.unimi.it/ ALOS Lab., University of Milan], Italy. 
* Prof. Csaba A. Moritz, [http://www.umass.edu/nanofabrics/ Nanoscale Computing Fabrics Lab., University of Massachusetts], USA 
* Prof. Kaushik Roy, [http://engineering.purdue.edu/NRL/index.html Nanoelectronics Research Lab., Purdue University], USA 
* Prof. Georgios Sirakoulis, [http://www.ee.duth.gr/en/ Department of Electrical and Computer Engineering, Democritus University of Thrace], Greece (''new partner'') 
* Prof. Mircea Stan, [http://hplp.ece.virginia.edu/home High-Performance Low-Power Lab., University of Virginia], USA 
* Prof. Mehdi B. Tahoori, [http://cdnc.itec.kit.edu/index.php Dependable Nano-Computing Group, Karlsruhe Institute of Technology], Germany

|- valign="top"
| '''funding agency & program''':
| width="500"| [http://ec.europa.eu/research/mariecurieactions/about-msca/actions/rise/index_en.htm European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)] [http://www.youtube.com/watch?v=dVeJFeKYrLs&feature=youtu.be RISE Video]
|- valign="top"
| '''budget''':
| 724.500 EURO
|- valign="top"
| '''duration''':
| 2015-2019
|}

{| style="margin-left: auto; margin-right: auto; border:1px solid #abd5f5; background:#CEDFE0; padding:0.2em 0.5em;"

|- valign=top
| |'''This project'''
* gathers globally leading research groups working on nanoelectronics and EDA;
* targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories; and
* contributes to the construction of emerging computers beyond CMOS by proposing nano-crossbar based computer architectures.
[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

[[Image:nanoxcomp_partners.png|center|none|450px|link=]]

|}

{|BORDER=0>
|-
<div><center>

'''PRESENTATIONS'''
<li style="display: inline-block;">


[[File:PPT.jpg|70px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]

</center></div>
|}

|}

----

<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.

| style="border:1px solid transparent;" |


| class="MainPageBG" style="width:50%; border:1px solid #BA55D3; background:#F8F8FF; vertical-align:top;"|
{| id="mp-right" style="width:100%; vertical-align:top; background:#F8F8FF;"
| style="padding:2px;" |

<h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project by the numbers, 2015-2019 </h2>
Started in 2015, the project has been successfully completed in 2019 with many achievements including:

* 34 researchers have been seconded to project partners, performing a total of 110,93 secondment months. 17 of them are early stage researchers and 9 of them are female researchers.

* 32 peer-reviewed papers contributed by 30 project secondees or partners. 12 of them are journal papers.

* 35 dissemination, outreach, and management activities have been performed.

|}

<h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project activity news </h2>

* We present our work "''Nano-Crossbar based Computing: Lessons Learned and Future Directions''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''CMOS Implementation of Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''Analog Neural Network based on Memristor Crossbar Arrays''" in [http://www.eleco.org.tr/ ELECO 2019].

* We present our work "''Noise-induced Performance Enhancement of Variability-aware Memristor Networks''" in [http://www.ieee-icecs2019.org/ ICECS 2019].

* We give a keynote talk "''Computing with Nano-crossbar Arrays''" in [http://www.iaria.org/conferences2019/CENICS19.html CENICS 2019].

* We present our work "''Testability of Switching Lattices in the Cellular Fault Model''" in [http://dsd-seaa2019.csd.auth.gr/ DSD 2019].

* A new partner Prof. Georgios Sirakoulis from Democritus University of Thrace, Greece has joined our consortium. Welcome!

* We present our work "''Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model''" in [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ LATS 2019].

* We present our work "''Testability of Switching Lattices in the Stuck at Fault Model''" in [http://vlsi-soc.di.univr.it/ VLSI-Soc 2018].

* We present our work "''Integrated Synthesis Methodology for Crossbar Arrays''" in a leading conference on nanocircuits/nanoarchitectures [http://www.nanoarch.org IEEE/ACM-NANOARCH 2018].

* We showcase our project in a [http://youtu.be/iwMSSvE1y8s YouTube video].

* We present our work "''Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2018].

* We present our work "''Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions''" in [http://icecs2017.org/ IEEE-ICECS 2017].

* We publicly introduce our project in [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event].


* We present our work "''Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis''" in [http://dsd-seaa2017.ocg.at/dsd2017 DSD 2017].

* We present our work "''Spintronic Memristor based Offset Cancellation Technique for Sense Amplifiers''" in [http://smacd2017.unisa.it/ SMACD 2017].

* We successfully have our midterm review meeting in Lausanne, Switzerland on March 2017. For the agenda [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | click here]].

* We present our work "''Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2017].


* We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016].

* We present our project and our work on ''logic synthesis of switching nanoarrays'' in [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 DSD 2016].

* We give an invited talk "''EU H2020 Success Story''" in [http://msca-association.teamwork.fr/en/programme H2020 MSCA 2016 Istanbul Training & Info Event].

* We present our work "''Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays''" in [http://www.isvlsi.org/ IEEE-ISVLSI 2016].

* We organize [http://sintesilogica.di.unimi.it/ the National Workshop on Logic Synthesis, July 2016] with introducing our project and preliminary research results.

* We give an invited talk "''Circuit Design and Optimization of Nano-Crossbar Arrays''" in [http://www.nanotr12.org/ NanoTR-12].

* We give a plenary talk "''Implementation of a Switching Nano-Crossbar Computer''" in [http://www.wseas.org/cms.action?id=11327 ACS 2016].

* We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry.


[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

<!--
----
<div style="margin-left:0.8em;">If interested, please contact [[Mustafa_Altun|Mustafa]]:
* '''email:''' altunmus@itu.edu.tr
* '''office:''' EEF 3005 (coffee guaranteed)</div> -
<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.->
|}
|}

Main Page

2020-01-27T12:35:33Z

Altun:

__NOTOC__

{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
|-
| colspan="2" style="background:#CEDFF2; text-align:center; padding:1px; border-bottom:1px #B8C7D9 solid;" |
<h2 style="margin:.5em; margin-top:.1em; border-bottom:1px; font-weight:bold;">
Welcome to the NANOxCOMP Project</h2>
|-
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;"  |

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer.

Project objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

[[Image:Research-nanoarray-1.png|center|none|800px|link=]]

<h2 id="mp-itn-h2" style="margin:0px; width:1010px; background:#F5F5F5; font-size:5%; font-weight:bold; border:0px solid #F5F5F5; text-align:left; color:#000; padding:0em 0em;"> </h2>

|}


{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"

| class="MainPageBG" style="width:50%; border:1px solid #B8C7D9; background:#8FBCCF; vertical-align:top; color:#000;" |
{| id="mp-left" style="width:100%; vertical-align:top; background:#F5F5F5;"

| style="padding:2px;" | <h2 id="mp-tafi-h2" style="margin:3px; background:#5F9EA0; font-size:125%; font-weight:bold; border:1px solid #4682B4; text-align:left; color:#000; padding:0.2em 0.4em;">Project details</h2>

{|
|- valign=top
| width="140" |'''title''':
| width="500"|Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
|- valign="top"
| width="140" |'''acronym''':
| width="500"|NANOxCOMP
|- valign="top"
| '''principal investigator / coordinator''':
| [http://www.ecc.itu.edu.tr/index.php?title=Mustafa_Altun Mustafa Altun], [http://www.ecc.itu.edu.tr/index.php?title=Main_Page ECC Group, Istanbul Technical University]
|- valign="top"
| '''partner(s)''':
| width="500"|
* Dr. Dan Alexandrescu, [http://www.iroctech.com/ IROC Techonogies], France 
* Prof. Lorena Anghel, [http://tima.imag.fr/tima/en/index.html TIMA Lab.], France (''partnership terminated'') 
* Prof. Valentina Ciriani, [http://alos.di.unimi.it/ ALOS Lab., University of Milan], Italy. 
* Prof. Csaba A. Moritz, [http://www.umass.edu/nanofabrics/ Nanoscale Computing Fabrics Lab., University of Massachusetts], USA 
* Prof. Kaushik Roy, [http://engineering.purdue.edu/NRL/index.html Nanoelectronics Research Lab., Purdue University], USA 
* Prof. Georgios Sirakoulis, [http://www.ee.duth.gr/en/ Department of Electrical and Computer Engineering, Democritus University of Thrace], Greece (''new partner'') 
* Prof. Mircea Stan, [http://hplp.ece.virginia.edu/home High-Performance Low-Power Lab., University of Virginia], USA 
* Prof. Mehdi B. Tahoori, [http://cdnc.itec.kit.edu/index.php Dependable Nano-Computing Group, Karlsruhe Institute of Technology], Germany

|- valign="top"
| '''funding agency & program''':
| width="500"| [http://ec.europa.eu/research/mariecurieactions/about-msca/actions/rise/index_en.htm European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)] [http://www.youtube.com/watch?v=dVeJFeKYrLs&feature=youtu.be RISE Video]
|- valign="top"
| '''budget''':
| 724.500 EURO
|- valign="top"
| '''duration''':
| 2015-2019
|}

{| style="margin-left: auto; margin-right: auto; border:1px solid #abd5f5; background:#CEDFE0; padding:0.2em 0.5em;"

|- valign=top
| |'''This project'''
* gathers globally leading research groups working on nanoelectronics and EDA;
* targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories; and
* contributes to the construction of emerging computers beyond CMOS by proposing nano-crossbar based computer architectures.
[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

[[Image:nanoxcomp_partners.png|center|none|450px|link=]]

|}

{|BORDER=0>
|-
<div><center>

'''PRESENTATIONS'''
<li style="display: inline-block;">


[[File:PPT.jpg|70px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]

</center></div>
|}

|}

----

<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.

| style="border:1px solid transparent;" |


| class="MainPageBG" style="width:50%; border:1px solid #BA55D3; background:#F8F8FF; vertical-align:top;"|
{| id="mp-right" style="width:100%; vertical-align:top; background:#F8F8FF;"
| style="padding:2px;" |

<h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project by the numbers, 2015-2019 </h2>
Started in 2015, the project has been successfully completed in 2019 with many achievements including:

* 34 researchers have been seconded to project partners, performing a total of 110,43 secondment months. 17 of them are early stage researchers and 9 of them are female researchers.

* 32 peer-reviewed papers contributed by 30 project secondees or partners. 12 of them are journal papers.

* 35 dissemination, outreach, and management activities have been performed.

|}

<h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project activity news </h2>

* We present our work "''Nano-Crossbar based Computing: Lessons Learned and Future Directions''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''CMOS Implementation of Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''Analog Neural Network based on Memristor Crossbar Arrays''" in [http://www.eleco.org.tr/ ELECO 2019].

* We present our work "''Noise-induced Performance Enhancement of Variability-aware Memristor Networks''" in [http://www.ieee-icecs2019.org/ ICECS 2019].

* We give a keynote talk "''Computing with Nano-crossbar Arrays''" in [http://www.iaria.org/conferences2019/CENICS19.html CENICS 2019].

* We present our work "''Testability of Switching Lattices in the Cellular Fault Model''" in [http://dsd-seaa2019.csd.auth.gr/ DSD 2019].

* A new partner Prof. Georgios Sirakoulis from Democritus University of Thrace, Greece has joined our consortium. Welcome!

* We present our work "''Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model''" in [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ LATS 2019].

* We present our work "''Testability of Switching Lattices in the Stuck at Fault Model''" in [http://vlsi-soc.di.univr.it/ VLSI-Soc 2018].

* We present our work "''Integrated Synthesis Methodology for Crossbar Arrays''" in a leading conference on nanocircuits/nanoarchitectures [http://www.nanoarch.org IEEE/ACM-NANOARCH 2018].

* We showcase our project in a [http://youtu.be/iwMSSvE1y8s YouTube video].

* We present our work "''Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2018].

* We present our work "''Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions''" in [http://icecs2017.org/ IEEE-ICECS 2017].

* We publicly introduce our project in [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event].


* We present our work "''Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis''" in [http://dsd-seaa2017.ocg.at/dsd2017 DSD 2017].

* We present our work "''Spintronic Memristor based Offset Cancellation Technique for Sense Amplifiers''" in [http://smacd2017.unisa.it/ SMACD 2017].

* We successfully have our midterm review meeting in Lausanne, Switzerland on March 2017. For the agenda [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | click here]].

* We present our work "''Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2017].


* We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016].

* We present our project and our work on ''logic synthesis of switching nanoarrays'' in [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 DSD 2016].

* We give an invited talk "''EU H2020 Success Story''" in [http://msca-association.teamwork.fr/en/programme H2020 MSCA 2016 Istanbul Training & Info Event].

* We present our work "''Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays''" in [http://www.isvlsi.org/ IEEE-ISVLSI 2016].

* We organize [http://sintesilogica.di.unimi.it/ the National Workshop on Logic Synthesis, July 2016] with introducing our project and preliminary research results.

* We give an invited talk "''Circuit Design and Optimization of Nano-Crossbar Arrays''" in [http://www.nanotr12.org/ NanoTR-12].

* We give a plenary talk "''Implementation of a Switching Nano-Crossbar Computer''" in [http://www.wseas.org/cms.action?id=11327 ACS 2016].

* We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry.


[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

<!--
----
<div style="margin-left:0.8em;">If interested, please contact [[Mustafa_Altun|Mustafa]]:
* '''email:''' altunmus@itu.edu.tr
* '''office:''' EEF 3005 (coffee guaranteed)</div> -
<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.->
|}
|}

Publications and Presentations

2020-01-22T15:45:40Z

Altun: /* Papers on Technology Development */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==


{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2020-01-22T15:45:16Z

Altun: /* Comprehensive Project Papers */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | CMOS Implementation of Switching Lattices]]
|- valign="top"
| '''authors''':
| Ismail Cevik, Levent Aksoy, and Mustafa Altun
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf]]
 
[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2020-01-21T12:42:52Z

Altun: /* Papers on Technology Development */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]
 
[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 Slides
|}
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | CMOS Implementation of Switching Lattices]]
|- valign="top"
| '''authors''':
| Ismail Cevik, Levent Aksoy, and Mustafa Altun
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf]]
 
[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

File:Cevik Aksoy Altun CMOS Implementation of Switching Lattices.pdf

2020-01-21T12:42:31Z

Altun:

Publications and Presentations

2020-01-21T12:42:16Z

Altun: /* Papers on Technology Development */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]
 
[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 Slides
|}
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | CMOS Implementation of Switching Lattices]]
|- valign="top"
| '''authors''':
| Ismail Cevik, Levent Aksoy, and Mustafa Altun
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/04/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf]]
 
[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2020-01-21T12:39:52Z

Altun: /* Comprehensive Project Papers */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]
 
[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 Slides
|}
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2020-01-21T12:39:29Z

Altun: /* Comprehensive Project Papers */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]
 
[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 Slides
|}
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

File:Altun EtAl NANOxCOMP Lessons Learned Future Directions.pdf

2020-01-21T12:38:58Z

Altun:

Publications and Presentations

2020-01-21T12:38:42Z

Altun: /* Comprehensive Project Papers */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]
 
[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 Slides
|}
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Main Page

2019-12-24T12:30:12Z

Altun:

__NOTOC__

{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
|-
| colspan="2" style="background:#CEDFF2; text-align:center; padding:1px; border-bottom:1px #B8C7D9 solid;" |
<h2 style="margin:.5em; margin-top:.1em; border-bottom:1px; font-weight:bold;">
Welcome to the NANOxCOMP Project</h2>
|-
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;"  |

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer.

Project objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

[[Image:Research-nanoarray-1.png|center|none|800px|link=]]

<h2 id="mp-itn-h2" style="margin:0px; width:1010px; background:#F5F5F5; font-size:5%; font-weight:bold; border:0px solid #F5F5F5; text-align:left; color:#000; padding:0em 0em;"> </h2>

|}


{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"

| class="MainPageBG" style="width:50%; border:1px solid #B8C7D9; background:#8FBCCF; vertical-align:top; color:#000;" |
{| id="mp-left" style="width:100%; vertical-align:top; background:#F5F5F5;"

| style="padding:2px;" | <h2 id="mp-tafi-h2" style="margin:3px; background:#5F9EA0; font-size:125%; font-weight:bold; border:1px solid #4682B4; text-align:left; color:#000; padding:0.2em 0.4em;">Project details</h2>

{|
|- valign=top
| width="140" |'''title''':
| width="500"|Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
|- valign="top"
| width="140" |'''acronym''':
| width="500"|NANOxCOMP
|- valign="top"
| '''principal investigator / coordinator''':
| [http://www.ecc.itu.edu.tr/index.php?title=Mustafa_Altun Mustafa Altun], [http://www.ecc.itu.edu.tr/index.php?title=Main_Page ECC Group, Istanbul Technical University]
|- valign="top"
| '''partner(s)''':
| width="500"|
* Dr. Dan Alexandrescu, [http://www.iroctech.com/ IROC Techonogies], France 
* Prof. Lorena Anghel, [http://tima.imag.fr/tima/en/index.html TIMA Lab.], France (''partnership terminated'') 
* Prof. Valentina Ciriani, [http://alos.di.unimi.it/ ALOS Lab., University of Milan], Italy. 
* Prof. Csaba A. Moritz, [http://www.umass.edu/nanofabrics/ Nanoscale Computing Fabrics Lab., University of Massachusetts], USA 
* Prof. Kaushik Roy, [http://engineering.purdue.edu/NRL/index.html Nanoelectronics Research Lab., Purdue University], USA 
* Prof. Georgios Sirakoulis, [http://www.ee.duth.gr/en/ Department of Electrical and Computer Engineering, Democritus University of Thrace], Greece (''new partner'') 
* Prof. Mircea Stan, [http://hplp.ece.virginia.edu/home High-Performance Low-Power Lab., University of Virginia], USA 
* Prof. Mehdi B. Tahoori, [http://cdnc.itec.kit.edu/index.php Dependable Nano-Computing Group, Karlsruhe Institute of Technology], Germany

|- valign="top"
| '''funding agency & program''':
| width="500"| [http://ec.europa.eu/research/mariecurieactions/about-msca/actions/rise/index_en.htm European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)] [http://www.youtube.com/watch?v=dVeJFeKYrLs&feature=youtu.be RISE Video]
|- valign="top"
| '''budget''':
| 724.500 EURO
|- valign="top"
| '''duration''':
| 2015-2019
|}

{| style="margin-left: auto; margin-right: auto; border:1px solid #abd5f5; background:#CEDFE0; padding:0.2em 0.5em;"

|- valign=top
| |'''This project'''
* gathers globally leading research groups working on nanoelectronics and EDA;
* targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories; and
* contributes to the construction of emerging computers beyond CMOS by proposing nano-crossbar based computer architectures.
[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

[[Image:nanoxcomp_partners.png|center|none|450px|link=]]

|}

{|BORDER=0>
|-
<div><center>

'''PRESENTATIONS'''
<li style="display: inline-block;">


[[File:PPT.jpg|70px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]

</center></div>
|}

|}

----

<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.

| style="border:1px solid transparent;" |


| class="MainPageBG" style="width:50%; border:1px solid #BA55D3; background:#F8F8FF; vertical-align:top;"|
{| id="mp-right" style="width:100%; vertical-align:top; background:#F8F8FF;"
| style="padding:2px;" |

<h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project by the numbers, 2015-2019 </h2>
Started in 2015, the project has been successfully completed in 2019 with many achievements including:

* 34 researchers have been seconded to project partners, performing a total of 110,93 secondment months. 17 of them are early stage researchers and 9 of them are female researchers.

* 32 peer-reviewed papers contributed by 30 project secondees or partners. 12 of them are journal papers.

* 35 dissemination, outreach, and management activities have been performed.

|}

<h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project activity news </h2>

* We present our work "''Nano-Crossbar based Computing: Lessons Learned and Future Directions''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''CMOS Implementation of Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''Analog Neural Network based on Memristor Crossbar Arrays''" in [http://www.eleco.org.tr/ ELECO 2019].

* We present our work "''Noise-induced Performance Enhancement of Variability-aware Memristor Networks''" in [http://www.ieee-icecs2019.org/ ICECS 2019].

* We give a keynote talk "''Computing with Nano-crossbar Arrays''" in [http://www.iaria.org/conferences2019/CENICS19.html CENICS 2019].

* We present our work "''Testability of Switching Lattices in the Cellular Fault Model''" in [http://dsd-seaa2019.csd.auth.gr/ DSD 2019].

* A new partner Prof. Georgios Sirakoulis from Democritus University of Thrace, Greece has joined our consortium. Welcome!

* We present our work "''Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model''" in [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ LATS 2019].

* We present our work "''Testability of Switching Lattices in the Stuck at Fault Model''" in [http://vlsi-soc.di.univr.it/ VLSI-Soc 2018].

* We present our work "''Integrated Synthesis Methodology for Crossbar Arrays''" in a leading conference on nanocircuits/nanoarchitectures [http://www.nanoarch.org IEEE/ACM-NANOARCH 2018].

* We showcase our project in a [http://youtu.be/iwMSSvE1y8s YouTube video].

* We present our work "''Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2018].

* We present our work "''Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions''" in [http://icecs2017.org/ IEEE-ICECS 2017].

* We publicly introduce our project in [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event].


* We present our work "''Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis''" in [http://dsd-seaa2017.ocg.at/dsd2017 DSD 2017].

* We present our work "''Spintronic Memristor based Offset Cancellation Technique for Sense Amplifiers''" in [http://smacd2017.unisa.it/ SMACD 2017].

* We successfully have our midterm review meeting in Lausanne, Switzerland on March 2017. For the agenda [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | click here]].

* We present our work "''Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2017].


* We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016].

* We present our project and our work on ''logic synthesis of switching nanoarrays'' in [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 DSD 2016].

* We give an invited talk "''EU H2020 Success Story''" in [http://msca-association.teamwork.fr/en/programme H2020 MSCA 2016 Istanbul Training & Info Event].

* We present our work "''Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays''" in [http://www.isvlsi.org/ IEEE-ISVLSI 2016].

* We organize [http://sintesilogica.di.unimi.it/ the National Workshop on Logic Synthesis, July 2016] with introducing our project and preliminary research results.

* We give an invited talk "''Circuit Design and Optimization of Nano-Crossbar Arrays''" in [http://www.nanotr12.org/ NanoTR-12].

* We give a plenary talk "''Implementation of a Switching Nano-Crossbar Computer''" in [http://www.wseas.org/cms.action?id=11327 ACS 2016].

* We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry.


[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

<!--
----
<div style="margin-left:0.8em;">If interested, please contact [[Mustafa_Altun|Mustafa]]:
* '''email:''' altunmus@itu.edu.tr
* '''office:''' EEF 3005 (coffee guaranteed)</div> -
<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.->
|}
|}

Main Page

2019-12-24T12:29:48Z

Altun:

__NOTOC__

{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
|-
| colspan="2" style="background:#CEDFF2; text-align:center; padding:1px; border-bottom:1px #B8C7D9 solid;" |
<h2 style="margin:.5em; margin-top:.1em; border-bottom:1px; font-weight:bold;">
Welcome to the NANOxCOMP Project</h2>
|-
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;"  |

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer.

Project objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

[[Image:Research-nanoarray-1.png|center|none|800px|link=]]

<h2 id="mp-itn-h2" style="margin:0px; width:1010px; background:#F5F5F5; font-size:5%; font-weight:bold; border:0px solid #F5F5F5; text-align:left; color:#000; padding:0em 0em;"> </h2>

|}


{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"

| class="MainPageBG" style="width:50%; border:1px solid #B8C7D9; background:#8FBCCF; vertical-align:top; color:#000;" |
{| id="mp-left" style="width:100%; vertical-align:top; background:#F5F5F5;"

| style="padding:2px;" | <h2 id="mp-tafi-h2" style="margin:3px; background:#5F9EA0; font-size:125%; font-weight:bold; border:1px solid #4682B4; text-align:left; color:#000; padding:0.2em 0.4em;">Project details</h2>

{|
|- valign=top
| width="140" |'''title''':
| width="500"|Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
|- valign="top"
| width="140" |'''acronym''':
| width="500"|NANOxCOMP
|- valign="top"
| '''principal investigator / coordinator''':
| [http://www.ecc.itu.edu.tr/index.php?title=Mustafa_Altun Mustafa Altun], [http://www.ecc.itu.edu.tr/index.php?title=Main_Page ECC Group, Istanbul Technical University]
|- valign="top"
| '''partner(s)''':
| width="500"|
* Dr. Dan Alexandrescu, [http://www.iroctech.com/ IROC Techonogies], France 
* Prof. Lorena Anghel, [http://tima.imag.fr/tima/en/index.html TIMA Lab.], France (''partnership terminated'') 
* Prof. Valentina Ciriani, [http://alos.di.unimi.it/ ALOS Lab., University of Milan], Italy. 
* Prof. Csaba A. Moritz, [http://www.umass.edu/nanofabrics/ Nanoscale Computing Fabrics Lab., University of Massachusetts], USA 
* Prof. Kaushik Roy, [http://engineering.purdue.edu/NRL/index.html Nanoelectronics Research Lab., Purdue University], USA 
* Prof. Georgios Sirakoulis, [http://www.ee.duth.gr/en/ Department of Electrical and Computer Engineering, Democritus University of Thrace], Greece (''new partner'') 
* Prof. Mircea Stan, [http://hplp.ece.virginia.edu/home High-Performance Low-Power Lab., University of Virginia], USA 
* Prof. Mehdi B. Tahoori, [http://cdnc.itec.kit.edu/index.php Dependable Nano-Computing Group, Karlsruhe Institute of Technology], Germany

|- valign="top"
| '''funding agency & program''':
| width="500"| [http://ec.europa.eu/research/mariecurieactions/about-msca/actions/rise/index_en.htm European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)] [http://www.youtube.com/watch?v=dVeJFeKYrLs&feature=youtu.be RISE Video]
|- valign="top"
| '''budget''':
| 724.500 EURO
|- valign="top"
| '''duration''':
| 2015-2019
|}

{| style="margin-left: auto; margin-right: auto; border:1px solid #abd5f5; background:#CEDFE0; padding:0.2em 0.5em;"

|- valign=top
| |'''This project'''
* gathers globally leading research groups working on nanoelectronics and EDA;
* targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories; and
* contributes to the construction of emerging computers beyond CMOS by proposing nano-crossbar based computer architectures.
[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

[[Image:nanoxcomp_partners.png|center|none|450px|link=]]

|}

{|BORDER=0>
|-
<div><center>

'''PRESENTATIONS'''
<li style="display: inline-block;">


[[File:PPT.jpg|70px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]

</center></div>
|}

|}

----

<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.

| style="border:1px solid transparent;" |


| class="MainPageBG" style="width:50%; border:1px solid #BA55D3; background:#F8F8FF; vertical-align:top;"|
{| id="mp-right" style="width:100%; vertical-align:top; background:#F8F8FF;"
| style="padding:2px;" |

<h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project by the numbers, 2015-2019 </h2>
Started in 2015, the project has been successfully completed in 2019 with many achievements including:

* 34 researchers have been seconded to project partners, performing a total of 110,93 secondment months. 17 of them are early stage researchers and 9 of them are female researchers.

* 32 peer-reviewed papers contributed by 30 project secondees or partners. 13 of them are solely '''made in ECC''' -- all authors are from our group. 12 of them are journal papers.

* 35 dissemination, outreach, and management activities have been performed.

|}

<h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project activity news </h2>

* We present our work "''Nano-Crossbar based Computing: Lessons Learned and Future Directions''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''CMOS Implementation of Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''Analog Neural Network based on Memristor Crossbar Arrays''" in [http://www.eleco.org.tr/ ELECO 2019].

* We present our work "''Noise-induced Performance Enhancement of Variability-aware Memristor Networks''" in [http://www.ieee-icecs2019.org/ ICECS 2019].

* We give a keynote talk "''Computing with Nano-crossbar Arrays''" in [http://www.iaria.org/conferences2019/CENICS19.html CENICS 2019].

* We present our work "''Testability of Switching Lattices in the Cellular Fault Model''" in [http://dsd-seaa2019.csd.auth.gr/ DSD 2019].

* A new partner Prof. Georgios Sirakoulis from Democritus University of Thrace, Greece has joined our consortium. Welcome!

* We present our work "''Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model''" in [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ LATS 2019].

* We present our work "''Testability of Switching Lattices in the Stuck at Fault Model''" in [http://vlsi-soc.di.univr.it/ VLSI-Soc 2018].

* We present our work "''Integrated Synthesis Methodology for Crossbar Arrays''" in a leading conference on nanocircuits/nanoarchitectures [http://www.nanoarch.org IEEE/ACM-NANOARCH 2018].

* We showcase our project in a [http://youtu.be/iwMSSvE1y8s YouTube video].

* We present our work "''Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2018].

* We present our work "''Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions''" in [http://icecs2017.org/ IEEE-ICECS 2017].

* We publicly introduce our project in [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event].


* We present our work "''Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis''" in [http://dsd-seaa2017.ocg.at/dsd2017 DSD 2017].

* We present our work "''Spintronic Memristor based Offset Cancellation Technique for Sense Amplifiers''" in [http://smacd2017.unisa.it/ SMACD 2017].

* We successfully have our midterm review meeting in Lausanne, Switzerland on March 2017. For the agenda [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | click here]].

* We present our work "''Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2017].


* We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016].

* We present our project and our work on ''logic synthesis of switching nanoarrays'' in [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 DSD 2016].

* We give an invited talk "''EU H2020 Success Story''" in [http://msca-association.teamwork.fr/en/programme H2020 MSCA 2016 Istanbul Training & Info Event].

* We present our work "''Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays''" in [http://www.isvlsi.org/ IEEE-ISVLSI 2016].

* We organize [http://sintesilogica.di.unimi.it/ the National Workshop on Logic Synthesis, July 2016] with introducing our project and preliminary research results.

* We give an invited talk "''Circuit Design and Optimization of Nano-Crossbar Arrays''" in [http://www.nanotr12.org/ NanoTR-12].

* We give a plenary talk "''Implementation of a Switching Nano-Crossbar Computer''" in [http://www.wseas.org/cms.action?id=11327 ACS 2016].

* We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry.


[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

<!--
----
<div style="margin-left:0.8em;">If interested, please contact [[Mustafa_Altun|Mustafa]]:
* '''email:''' altunmus@itu.edu.tr
* '''office:''' EEF 3005 (coffee guaranteed)</div> -
<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.->
|}
|}

Main Page

2019-12-24T12:01:41Z

Altun:

__NOTOC__

{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
|-
| colspan="2" style="background:#CEDFF2; text-align:center; padding:1px; border-bottom:1px #B8C7D9 solid;" |
<h2 style="margin:.5em; margin-top:.1em; border-bottom:1px; font-weight:bold;">
Welcome to the NANOxCOMP Project</h2>
|-
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;"  |

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer.

Project objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

[[Image:Research-nanoarray-1.png|center|none|800px|link=]]

<h2 id="mp-itn-h2" style="margin:0px; width:1010px; background:#F5F5F5; font-size:5%; font-weight:bold; border:0px solid #F5F5F5; text-align:left; color:#000; padding:0em 0em;"> </h2>

|}


{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"

| class="MainPageBG" style="width:50%; border:1px solid #B8C7D9; background:#8FBCCF; vertical-align:top; color:#000;" |
{| id="mp-left" style="width:100%; vertical-align:top; background:#F5F5F5;"

| style="padding:2px;" | <h2 id="mp-tafi-h2" style="margin:3px; background:#5F9EA0; font-size:125%; font-weight:bold; border:1px solid #4682B4; text-align:left; color:#000; padding:0.2em 0.4em;">Project details</h2>

{|
|- valign=top
| width="140" |'''title''':
| width="500"|Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
|- valign="top"
| width="140" |'''acronym''':
| width="500"|NANOxCOMP
|- valign="top"
| '''principal investigator / coordinator''':
| [http://www.ecc.itu.edu.tr/index.php?title=Mustafa_Altun Mustafa Altun], [http://www.ecc.itu.edu.tr/index.php?title=Main_Page ECC Group, Istanbul Technical University]
|- valign="top"
| '''partner(s)''':
| width="500"|
* Dr. Dan Alexandrescu, [http://www.iroctech.com/ IROC Techonogies], France 
* Prof. Lorena Anghel, [http://tima.imag.fr/tima/en/index.html TIMA Lab.], France (''partnership terminated'') 
* Prof. Valentina Ciriani, [http://alos.di.unimi.it/ ALOS Lab., University of Milan], Italy. 
* Prof. Csaba A. Moritz, [http://www.umass.edu/nanofabrics/ Nanoscale Computing Fabrics Lab., University of Massachusetts], USA 
* Prof. Kaushik Roy, [http://engineering.purdue.edu/NRL/index.html Nanoelectronics Research Lab., Purdue University], USA 
* Prof. Georgios Sirakoulis, [http://www.ee.duth.gr/en/ Department of Electrical and Computer Engineering, Democritus University of Thrace], Greece (''new partner'') 
* Prof. Mircea Stan, [http://hplp.ece.virginia.edu/home High-Performance Low-Power Lab., University of Virginia], USA 
* Prof. Mehdi B. Tahoori, [http://cdnc.itec.kit.edu/index.php Dependable Nano-Computing Group, Karlsruhe Institute of Technology], Germany

|- valign="top"
| '''funding agency & program''':
| width="500"| [http://ec.europa.eu/research/mariecurieactions/about-msca/actions/rise/index_en.htm European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)] [http://www.youtube.com/watch?v=dVeJFeKYrLs&feature=youtu.be RISE Video]
|- valign="top"
| '''budget''':
| 724.500 EURO
|- valign="top"
| '''duration''':
| 2015-2019
|}

{| style="margin-left: auto; margin-right: auto; border:1px solid #abd5f5; background:#CEDFE0; padding:0.2em 0.5em;"

|- valign=top
| |'''This project'''
* gathers globally leading research groups working on nanoelectronics and EDA;
* targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories; and
* contributes to the construction of emerging computers beyond CMOS by proposing nano-crossbar based computer architectures.
[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

[[Image:nanoxcomp_partners.png|center|none|450px|link=]]

|}

{|BORDER=0>
|-
<div><center>

'''PRESENTATIONS'''
<li style="display: inline-block;">


[[File:PPT.jpg|70px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]

</center></div>
|}

|}

----

<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.

| style="border:1px solid transparent;" |


| class="MainPageBG" style="width:50%; border:1px solid #BA55D3; background:#F8F8FF; vertical-align:top;"|
{| id="mp-right" style="width:100%; vertical-align:top; background:#F8F8FF;"
| style="padding:2px;" |

<h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project by the numbers, 2015-2019 </h2>
Started in 2015, the project has been successfully completed in 2019 with many achievements including:

* 1.300.000 TL/$450.000 was received to be spent for our group. $300.000 came from an '''EU H2020''' project and $150.000 came from three different '''TUBITAK''' projects. We are the principal investigator ('''PI''') of all these 4 projects.

* 20 peer-reviewed papers were published/accepted. 13 of them are solely '''made in ECC''' -- all authors are from our group. 4 of them are coauthored by our collaborators from '''industry''' and 5 of them are coauthored by our collaborators from '''academia'''.

* 5 '''Masters''' students graduated from our group and 5 '''Doctoral''' students joined us.

|}

<h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project activity news </h2>

* We present our work "''Nano-Crossbar based Computing: Lessons Learned and Future Directions''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''CMOS Implementation of Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''Analog Neural Network based on Memristor Crossbar Arrays''" in [http://www.eleco.org.tr/ ELECO 2019].

* We present our work "''Noise-induced Performance Enhancement of Variability-aware Memristor Networks''" in [http://www.ieee-icecs2019.org/ ICECS 2019].

* We give a keynote talk "''Computing with Nano-crossbar Arrays''" in [http://www.iaria.org/conferences2019/CENICS19.html CENICS 2019].

* We present our work "''Testability of Switching Lattices in the Cellular Fault Model''" in [http://dsd-seaa2019.csd.auth.gr/ DSD 2019].

* A new partner Prof. Georgios Sirakoulis from Democritus University of Thrace, Greece has joined our consortium. Welcome!

* We present our work "''Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model''" in [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ LATS 2019].

* We present our work "''Testability of Switching Lattices in the Stuck at Fault Model''" in [http://vlsi-soc.di.univr.it/ VLSI-Soc 2018].

* We present our work "''Integrated Synthesis Methodology for Crossbar Arrays''" in a leading conference on nanocircuits/nanoarchitectures [http://www.nanoarch.org IEEE/ACM-NANOARCH 2018].

* We showcase our project in a [http://youtu.be/iwMSSvE1y8s YouTube video].

* We present our work "''Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2018].

* We present our work "''Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions''" in [http://icecs2017.org/ IEEE-ICECS 2017].

* We publicly introduce our project in [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event].


* We present our work "''Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis''" in [http://dsd-seaa2017.ocg.at/dsd2017 DSD 2017].

* We present our work "''Spintronic Memristor based Offset Cancellation Technique for Sense Amplifiers''" in [http://smacd2017.unisa.it/ SMACD 2017].

* We successfully have our midterm review meeting in Lausanne, Switzerland on March 2017. For the agenda [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | click here]].

* We present our work "''Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2017].


* We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016].

* We present our project and our work on ''logic synthesis of switching nanoarrays'' in [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 DSD 2016].

* We give an invited talk "''EU H2020 Success Story''" in [http://msca-association.teamwork.fr/en/programme H2020 MSCA 2016 Istanbul Training & Info Event].

* We present our work "''Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays''" in [http://www.isvlsi.org/ IEEE-ISVLSI 2016].

* We organize [http://sintesilogica.di.unimi.it/ the National Workshop on Logic Synthesis, July 2016] with introducing our project and preliminary research results.

* We give an invited talk "''Circuit Design and Optimization of Nano-Crossbar Arrays''" in [http://www.nanotr12.org/ NanoTR-12].

* We give a plenary talk "''Implementation of a Switching Nano-Crossbar Computer''" in [http://www.wseas.org/cms.action?id=11327 ACS 2016].

* We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry.


[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

<!--
----
<div style="margin-left:0.8em;">If interested, please contact [[Mustafa_Altun|Mustafa]]:
* '''email:''' altunmus@itu.edu.tr
* '''office:''' EEF 3005 (coffee guaranteed)</div> -
<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.->
|}
|}

File:Yildiz Crossbar Analog Neural Network.pdf

2019-12-18T13:11:35Z

Altun: Altun uploaded a new version of "File:Yildiz Crossbar Analog Neural Network.pdf"

Activities

2019-12-09T14:24:18Z

Altun: /* Presentations of Published Papers */

==Presentations of Published Papers==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Noise-induced Performance Enhancement of Variability-aware Memristor Networks / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Vasileios Ntinas (DUTH) and Georigos Sirakoulis (DUTH)
|- valign=top
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Analog Neural Network based on Memristor Crossbar Arrays / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Hacer Yildiz (ITU) and Dogus Gungordu (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|- valign="top"
| '''people reached''':
|Over 300 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [[Media:Yildiz_Crossbar_Analog_Neural_Network.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Cellular Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Fault Mitigation of Switching Lattices under the Stuck-At Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|- valign="top"
| '''people reached''':
|Over 100 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Levent Aksoy (ITU), Serzat Safaltin (ITU), Mustafa Altun (ITU), and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Serzat Safaltin (ITU), Mustafa Altun (ITU), Valentina Ciriani (UMIL), and Levent Aksoy (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Stuck at Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|- valign="top"
| '''people reached''':
|Over 400 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]
 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Integrated Synthesis Methodology for Crossbar Arrays / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Ioana Vatajelu (INPG) and Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|- valign="top"
| '''people reached''':
|Over 300 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis and Defect Tolerance for Memristive Crossbar Array / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi, Valentina Ciriani (UMIL), and Gabriella Trucco (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mesut Atasoyu (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Mustafa Altun (ITU) – Kaushik Roy (PURDUE), Mircea Stan (UVA), Lorena Anghel (INPG), and Mehdi Tahoori (KIT)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Lausanne, Switzerland, 27-31 March 2017.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.
|}
| align=center width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://ati.ttu.ee/vlsi-soc2016/ IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, ESTONIA, 26-28 September 2016
|- valign="top"
| '''people reached''':
| Over 200 attendees mostly from academia.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis and Performance Optimization of a Switching Nano-crossbar Computer / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis for Switching Lattices by Decomposition with P-Circuits / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays / Poster
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Ceylan Morgul (ITU), Furkan Peker (ITU), and Mustafa Altun (ITU) - Mircea Stan (UVA)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, Pennsylvania, USA, 11-13 July 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

==Demonstrations and Exhibitions==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="402"| Journey of Computation and Nanocomputers / Demonstration and Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="402"| Tuba Ayhan (ITU), Mustafa Altun (ITU), Ceylan Morgul (ITU), Ensar Vahapoglu (ITU), Ismail Cevik (ITU), and Lida Kouhalvandi (ITU)
|- valign=top
| '''presented at''':
| width="402" | [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event]. Istanbul, Turkey 2017.
|- valign="top"
| '''people reached''':
| width="402" | Over 1000 attendees, mostly elementary and high school students, and general public.
|}
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/6/63/Altu_EU_NIGHT_Event-2017.pptx]]

 [[Media:Altu_EU_NIGHT_Event-2017.pptx | Slides-1]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fb/Ayhan_eu_night_hesaplama.pptx]]

 [[Media:ayhan_eu_night_hesaplama.pptx | Slides-2 ]]
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/81/Eu_night_poster.pdf]]

 [[Media:eu_night_poster.pdf | Poster]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="475"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Exhibition (Posters, Fliers and Slides)
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="475"| Mustafa Altun (ITU), Ceylan Morgul (ITU), and Onur Tunali (ITU) - Lorena Anghel (INPG) and Mehdi Tahoori (KIT)
|- valign="top"
|'''presented at''':
| width="475"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 2016.
|- valign="top"
|'''people reached''':
|Over 1000 attendees both from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]
|}

==Invited Talks ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays / Keynote Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.iaria.org/conferences2019/CENICS19.html The Twelfth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS'19)], Nice, France, 27-31 October 2019.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/8d/Altun_CENICS-2019.pptx]]

 [[Media:Altun_CENICS-2019.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Future and Emerging Computing Paradigms in Electronics / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://icecs2017.org/ 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)], Batumi, Georgia, 5-8 December 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/ff/Altun_ICECS-2017.pptx]]

 [[Media:Altun_ICECS-2017.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP / Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://sintesilogica.di.unimi.it/ National Workshop on Logic Synthesis (Organized)], Pisa, Italy, 5 July 2016
|- valign="top"
| '''people reached''':
|Over 50 attendees mostly from academia.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="476"| EU H2020 Success Story / Invited Talk
|- valign="top"
| width="1" | '''presenter(s)''':
| width="476"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="476"| [http://msca-association.teamwork.fr/index.php H2020 MSCA 2016 Istanbul Training & Info Event], Istanbul, Turkey, 13 June 2016
|- valign="top"
| '''people reached''':
| width="476"|Over 200 attendees from universities and research institutes (open to general public).
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Altun_MCSA_Info_Day-2016.pptx]]

 [[Media:Altun_MCSA_Info_Day-2016.pptx | Slides]]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/1/12/H2020_MCSA_Info_Day_Program_2016.pdf]]

 [[Media:H2020_MCSA_Info_Day_Program_2016.pdf | Program]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Circuit Design and Optimization of Nano-Crossbar Arrays / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://nanotr.org/en/ 12th Nanoscience and Nanotechnology Conference (NanoTR-12)], Kocaeli, Turkey, 3-5 June 2016.
|- valign="top"
| '''people reached''':
|Over 500 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/3/37/Altun_NanoTR12-2016.pptx]]

 [[Media:Altun_NanoTR12-2016.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Implementation of a Switching Nano-Crossbar Computer / Plenary Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.wseas.org/cms.action?id=11327 16th International Conference on APPLIED COMPUTER SCIENCE (ACS '16)], Istanbul, Turkey, 15-17 April 2016.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b2/Altun_ACT-2016.pptx]]

 [[Media:Altun_ACT-2016.pptx | Slides]]
|}

== Online Showcasing ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Video
|- valign="top"
| width="1" | '''prepared by''':
| width="550"| Mustafa Altun (ITU) and Ceylan Morgul (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://youtu.be/iwMSSvE1y8s YouTube].
|- valign="top"
|}
| align=center width="70" |

[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]
|}

== Magazine/Bulletin Columns ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Success Story from ITU - NANOxCOMP Project] / Article in a National Bulletin
|- valign="top"
| width="1" | '''author''':
| width="550"| Mustafa Altun (ITU)
|- valign=top
| '''appeared in''':
| [http://www.abmerkezi-arastirma.itu.edu.tr/yayinlarimiz/haber-bultenleri ITU Bulletin], September, Issue:5, 2017.
|- valign="top"
| '''people reached''':
| Publicly open, especially for university communities in Turkey.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2]]

 [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Bulletin]
|}

==Major Meetings of Project Personnel==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU) and Valentina Ciriani (UMIL).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 28 March 2019.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Valentina Ciriani (UMIL), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 20 March 2018.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/5/55/691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf]]

 [[Media:691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Midterm Review Meeting
|- valign="top"
| '''attendants''':
| width="550"| All project beneficiaries, the third country partner Mircea Stan, and almost all secondees attended.
|- valign="top"
| '''place''':
| width="550"| Lausanne, Switzerland, 27 March 2017.
|- valign="top"
| '''people reached''':
|Private meeting with the EU H2020 RISE Program representatives.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/4/45/1-691178-NANOxCOMP-MTM-agenda.pdf]]

 [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 15 March 2016.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

Publications and Presentations

2019-12-09T14:24:17Z

Altun: /* Papers on Fault Tolerance, Performance Modeling and Optimization */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Activities

2019-12-09T14:20:42Z

Altun: /* Presentations of Published Papers */

==Presentations of Published Papers==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Noise-induced Performance Enhancement of Variability-aware Memristor Networks / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Vasileios Ntinas (DUTH) and Georigos Sirakoulis (DUTH)
|- valign=top
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Cellular Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Fault Mitigation of Switching Lattices under the Stuck-At Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|- valign="top"
| '''people reached''':
|Over 100 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Levent Aksoy (ITU), Serzat Safaltin (ITU), Mustafa Altun (ITU), and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Serzat Safaltin (ITU), Mustafa Altun (ITU), Valentina Ciriani (UMIL), and Levent Aksoy (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Stuck at Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|- valign="top"
| '''people reached''':
|Over 400 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]
 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Integrated Synthesis Methodology for Crossbar Arrays / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Ioana Vatajelu (INPG) and Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|- valign="top"
| '''people reached''':
|Over 300 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis and Defect Tolerance for Memristive Crossbar Array / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi, Valentina Ciriani (UMIL), and Gabriella Trucco (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mesut Atasoyu (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Mustafa Altun (ITU) – Kaushik Roy (PURDUE), Mircea Stan (UVA), Lorena Anghel (INPG), and Mehdi Tahoori (KIT)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Lausanne, Switzerland, 27-31 March 2017.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.
|}
| align=center width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://ati.ttu.ee/vlsi-soc2016/ IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, ESTONIA, 26-28 September 2016
|- valign="top"
| '''people reached''':
| Over 200 attendees mostly from academia.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis and Performance Optimization of a Switching Nano-crossbar Computer / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis for Switching Lattices by Decomposition with P-Circuits / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays / Poster
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Ceylan Morgul (ITU), Furkan Peker (ITU), and Mustafa Altun (ITU) - Mircea Stan (UVA)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, Pennsylvania, USA, 11-13 July 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

==Demonstrations and Exhibitions==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="402"| Journey of Computation and Nanocomputers / Demonstration and Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="402"| Tuba Ayhan (ITU), Mustafa Altun (ITU), Ceylan Morgul (ITU), Ensar Vahapoglu (ITU), Ismail Cevik (ITU), and Lida Kouhalvandi (ITU)
|- valign=top
| '''presented at''':
| width="402" | [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event]. Istanbul, Turkey 2017.
|- valign="top"
| '''people reached''':
| width="402" | Over 1000 attendees, mostly elementary and high school students, and general public.
|}
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/6/63/Altu_EU_NIGHT_Event-2017.pptx]]

 [[Media:Altu_EU_NIGHT_Event-2017.pptx | Slides-1]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fb/Ayhan_eu_night_hesaplama.pptx]]

 [[Media:ayhan_eu_night_hesaplama.pptx | Slides-2 ]]
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/81/Eu_night_poster.pdf]]

 [[Media:eu_night_poster.pdf | Poster]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="475"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Exhibition (Posters, Fliers and Slides)
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="475"| Mustafa Altun (ITU), Ceylan Morgul (ITU), and Onur Tunali (ITU) - Lorena Anghel (INPG) and Mehdi Tahoori (KIT)
|- valign="top"
|'''presented at''':
| width="475"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 2016.
|- valign="top"
|'''people reached''':
|Over 1000 attendees both from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]
|}

==Invited Talks ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays / Keynote Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.iaria.org/conferences2019/CENICS19.html The Twelfth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS'19)], Nice, France, 27-31 October 2019.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/8d/Altun_CENICS-2019.pptx]]

 [[Media:Altun_CENICS-2019.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Future and Emerging Computing Paradigms in Electronics / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://icecs2017.org/ 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)], Batumi, Georgia, 5-8 December 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/ff/Altun_ICECS-2017.pptx]]

 [[Media:Altun_ICECS-2017.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP / Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://sintesilogica.di.unimi.it/ National Workshop on Logic Synthesis (Organized)], Pisa, Italy, 5 July 2016
|- valign="top"
| '''people reached''':
|Over 50 attendees mostly from academia.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="476"| EU H2020 Success Story / Invited Talk
|- valign="top"
| width="1" | '''presenter(s)''':
| width="476"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="476"| [http://msca-association.teamwork.fr/index.php H2020 MSCA 2016 Istanbul Training & Info Event], Istanbul, Turkey, 13 June 2016
|- valign="top"
| '''people reached''':
| width="476"|Over 200 attendees from universities and research institutes (open to general public).
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Altun_MCSA_Info_Day-2016.pptx]]

 [[Media:Altun_MCSA_Info_Day-2016.pptx | Slides]]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/1/12/H2020_MCSA_Info_Day_Program_2016.pdf]]

 [[Media:H2020_MCSA_Info_Day_Program_2016.pdf | Program]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Circuit Design and Optimization of Nano-Crossbar Arrays / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://nanotr.org/en/ 12th Nanoscience and Nanotechnology Conference (NanoTR-12)], Kocaeli, Turkey, 3-5 June 2016.
|- valign="top"
| '''people reached''':
|Over 500 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/3/37/Altun_NanoTR12-2016.pptx]]

 [[Media:Altun_NanoTR12-2016.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Implementation of a Switching Nano-Crossbar Computer / Plenary Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.wseas.org/cms.action?id=11327 16th International Conference on APPLIED COMPUTER SCIENCE (ACS '16)], Istanbul, Turkey, 15-17 April 2016.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b2/Altun_ACT-2016.pptx]]

 [[Media:Altun_ACT-2016.pptx | Slides]]
|}

== Online Showcasing ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Video
|- valign="top"
| width="1" | '''prepared by''':
| width="550"| Mustafa Altun (ITU) and Ceylan Morgul (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://youtu.be/iwMSSvE1y8s YouTube].
|- valign="top"
|}
| align=center width="70" |

[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]
|}

== Magazine/Bulletin Columns ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Success Story from ITU - NANOxCOMP Project] / Article in a National Bulletin
|- valign="top"
| width="1" | '''author''':
| width="550"| Mustafa Altun (ITU)
|- valign=top
| '''appeared in''':
| [http://www.abmerkezi-arastirma.itu.edu.tr/yayinlarimiz/haber-bultenleri ITU Bulletin], September, Issue:5, 2017.
|- valign="top"
| '''people reached''':
| Publicly open, especially for university communities in Turkey.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2]]

 [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Bulletin]
|}

==Major Meetings of Project Personnel==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU) and Valentina Ciriani (UMIL).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 28 March 2019.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Valentina Ciriani (UMIL), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 20 March 2018.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/5/55/691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf]]

 [[Media:691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Midterm Review Meeting
|- valign="top"
| '''attendants''':
| width="550"| All project beneficiaries, the third country partner Mircea Stan, and almost all secondees attended.
|- valign="top"
| '''place''':
| width="550"| Lausanne, Switzerland, 27 March 2017.
|- valign="top"
| '''people reached''':
|Private meeting with the EU H2020 RISE Program representatives.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/4/45/1-691178-NANOxCOMP-MTM-agenda.pdf]]

 [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 15 March 2016.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

Activities

2019-12-09T14:18:42Z

Altun: /* Presentations of Published Papers */

==Presentations of Published Papers==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Noise-induced Performance Enhancement of Variability-aware Memristor Networks / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Vasileios Ntinas (DUTH) and Georigos Sirakoulis (DUTH)
|- valign=top
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Cellular Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Fault Mitigation of Switching Lattices under the Stuck-At Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|- valign="top"
| '''people reached''':
|Over 100 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Levent Aksoy (ITU), Serzat Safaltin (ITU), Mustafa Altun (ITU), and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Serzat Safaltin (ITU), Mustafa Altun (ITU), Valentina Ciriani (UMIL), and Levent Aksoy (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Stuck at Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|- valign="top"
| '''people reached''':
|Over 400 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]
 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Integrated Synthesis Methodology for Crossbar Arrays / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Ioana Vatajelu (INPG) and Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|- valign="top"
| '''people reached''':
|Over 300 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis and Defect Tolerance for Memristive Crossbar Array / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi, Valentina Ciriani (UMIL), and Gabriella Trucco (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mesut Atasoyu (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Mustafa Altun (ITU) – Kaushik Roy (PURDUE), Mircea Stan (UVA), Lorena Anghel (INPG), and Mehdi Tahoori (KIT)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Lausanne, Switzerland, 27-31 March 2017.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.
|}
| align=center width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://ati.ttu.ee/vlsi-soc2016/ IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, ESTONIA, 26-28 September 2016
|- valign="top"
| '''people reached''':
| Over 200 attendees mostly from academia.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis and Performance Optimization of a Switching Nano-crossbar Computer / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis for Switching Lattices by Decomposition with P-Circuits / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays / Poster
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Ceylan Morgul (ITU), Furkan Peker (ITU), and Mustafa Altun (ITU) - Mircea Stan (UVA)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, Pennsylvania, USA, 11-13 July 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

==Demonstrations and Exhibitions==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="402"| Journey of Computation and Nanocomputers / Demonstration and Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="402"| Tuba Ayhan (ITU), Mustafa Altun (ITU), Ceylan Morgul (ITU), Ensar Vahapoglu (ITU), Ismail Cevik (ITU), and Lida Kouhalvandi (ITU)
|- valign=top
| '''presented at''':
| width="402" | [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event]. Istanbul, Turkey 2017.
|- valign="top"
| '''people reached''':
| width="402" | Over 1000 attendees, mostly elementary and high school students, and general public.
|}
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/6/63/Altu_EU_NIGHT_Event-2017.pptx]]

 [[Media:Altu_EU_NIGHT_Event-2017.pptx | Slides-1]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fb/Ayhan_eu_night_hesaplama.pptx]]

 [[Media:ayhan_eu_night_hesaplama.pptx | Slides-2 ]]
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/81/Eu_night_poster.pdf]]

 [[Media:eu_night_poster.pdf | Poster]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="475"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Exhibition (Posters, Fliers and Slides)
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="475"| Mustafa Altun (ITU), Ceylan Morgul (ITU), and Onur Tunali (ITU) - Lorena Anghel (INPG) and Mehdi Tahoori (KIT)
|- valign="top"
|'''presented at''':
| width="475"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 2016.
|- valign="top"
|'''people reached''':
|Over 1000 attendees both from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]
|}

==Invited Talks ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays / Keynote Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.iaria.org/conferences2019/CENICS19.html The Twelfth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS'19)], Nice, France, 27-31 October 2019.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/8d/Altun_CENICS-2019.pptx]]

 [[Media:Altun_CENICS-2019.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Future and Emerging Computing Paradigms in Electronics / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://icecs2017.org/ 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)], Batumi, Georgia, 5-8 December 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/ff/Altun_ICECS-2017.pptx]]

 [[Media:Altun_ICECS-2017.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP / Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://sintesilogica.di.unimi.it/ National Workshop on Logic Synthesis (Organized)], Pisa, Italy, 5 July 2016
|- valign="top"
| '''people reached''':
|Over 50 attendees mostly from academia.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="476"| EU H2020 Success Story / Invited Talk
|- valign="top"
| width="1" | '''presenter(s)''':
| width="476"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="476"| [http://msca-association.teamwork.fr/index.php H2020 MSCA 2016 Istanbul Training & Info Event], Istanbul, Turkey, 13 June 2016
|- valign="top"
| '''people reached''':
| width="476"|Over 200 attendees from universities and research institutes (open to general public).
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Altun_MCSA_Info_Day-2016.pptx]]

 [[Media:Altun_MCSA_Info_Day-2016.pptx | Slides]]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/1/12/H2020_MCSA_Info_Day_Program_2016.pdf]]

 [[Media:H2020_MCSA_Info_Day_Program_2016.pdf | Program]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Circuit Design and Optimization of Nano-Crossbar Arrays / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://nanotr.org/en/ 12th Nanoscience and Nanotechnology Conference (NanoTR-12)], Kocaeli, Turkey, 3-5 June 2016.
|- valign="top"
| '''people reached''':
|Over 500 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/3/37/Altun_NanoTR12-2016.pptx]]

 [[Media:Altun_NanoTR12-2016.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Implementation of a Switching Nano-Crossbar Computer / Plenary Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.wseas.org/cms.action?id=11327 16th International Conference on APPLIED COMPUTER SCIENCE (ACS '16)], Istanbul, Turkey, 15-17 April 2016.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b2/Altun_ACT-2016.pptx]]

 [[Media:Altun_ACT-2016.pptx | Slides]]
|}

== Online Showcasing ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Video
|- valign="top"
| width="1" | '''prepared by''':
| width="550"| Mustafa Altun (ITU) and Ceylan Morgul (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://youtu.be/iwMSSvE1y8s YouTube].
|- valign="top"
|}
| align=center width="70" |

[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]
|}

== Magazine/Bulletin Columns ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Success Story from ITU - NANOxCOMP Project] / Article in a National Bulletin
|- valign="top"
| width="1" | '''author''':
| width="550"| Mustafa Altun (ITU)
|- valign=top
| '''appeared in''':
| [http://www.abmerkezi-arastirma.itu.edu.tr/yayinlarimiz/haber-bultenleri ITU Bulletin], September, Issue:5, 2017.
|- valign="top"
| '''people reached''':
| Publicly open, especially for university communities in Turkey.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2]]

 [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Bulletin]
|}

==Major Meetings of Project Personnel==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU) and Valentina Ciriani (UMIL).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 28 March 2019.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Valentina Ciriani (UMIL), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 20 March 2018.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/5/55/691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf]]

 [[Media:691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Midterm Review Meeting
|- valign="top"
| '''attendants''':
| width="550"| All project beneficiaries, the third country partner Mircea Stan, and almost all secondees attended.
|- valign="top"
| '''place''':
| width="550"| Lausanne, Switzerland, 27 March 2017.
|- valign="top"
| '''people reached''':
|Private meeting with the EU H2020 RISE Program representatives.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/4/45/1-691178-NANOxCOMP-MTM-agenda.pdf]]

 [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 15 March 2016.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

Activities

2019-12-09T14:17:55Z

Altun: /* Presentations of Published Papers */

==Presentations of Published Papers==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Noise-induced Performance Enhancement of Variability-aware Memristor Networks / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Vasileios Ntinas (DUTH) and Georigos Sirakoulis (DUTH)
|- valign=top
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]

 [http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Cellular Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Fault Mitigation of Switching Lattices under the Stuck-At Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|- valign="top"
| '''people reached''':
|Over 100 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Levent Aksoy (ITU), Serzat Safaltin (ITU), Mustafa Altun (ITU), and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Serzat Safaltin (ITU), Mustafa Altun (ITU), Valentina Ciriani (UMIL), and Levent Aksoy (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Stuck at Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|- valign="top"
| '''people reached''':
|Over 400 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]
 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Integrated Synthesis Methodology for Crossbar Arrays / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Ioana Vatajelu (INPG) and Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|- valign="top"
| '''people reached''':
|Over 300 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis and Defect Tolerance for Memristive Crossbar Array / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi, Valentina Ciriani (UMIL), and Gabriella Trucco (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mesut Atasoyu (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Mustafa Altun (ITU) – Kaushik Roy (PURDUE), Mircea Stan (UVA), Lorena Anghel (INPG), and Mehdi Tahoori (KIT)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Lausanne, Switzerland, 27-31 March 2017.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.
|}
| align=center width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://ati.ttu.ee/vlsi-soc2016/ IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, ESTONIA, 26-28 September 2016
|- valign="top"
| '''people reached''':
| Over 200 attendees mostly from academia.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis and Performance Optimization of a Switching Nano-crossbar Computer / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis for Switching Lattices by Decomposition with P-Circuits / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays / Poster
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Ceylan Morgul (ITU), Furkan Peker (ITU), and Mustafa Altun (ITU) - Mircea Stan (UVA)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, Pennsylvania, USA, 11-13 July 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

==Demonstrations and Exhibitions==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="402"| Journey of Computation and Nanocomputers / Demonstration and Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="402"| Tuba Ayhan (ITU), Mustafa Altun (ITU), Ceylan Morgul (ITU), Ensar Vahapoglu (ITU), Ismail Cevik (ITU), and Lida Kouhalvandi (ITU)
|- valign=top
| '''presented at''':
| width="402" | [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event]. Istanbul, Turkey 2017.
|- valign="top"
| '''people reached''':
| width="402" | Over 1000 attendees, mostly elementary and high school students, and general public.
|}
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/6/63/Altu_EU_NIGHT_Event-2017.pptx]]

 [[Media:Altu_EU_NIGHT_Event-2017.pptx | Slides-1]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fb/Ayhan_eu_night_hesaplama.pptx]]

 [[Media:ayhan_eu_night_hesaplama.pptx | Slides-2 ]]
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/81/Eu_night_poster.pdf]]

 [[Media:eu_night_poster.pdf | Poster]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="475"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Exhibition (Posters, Fliers and Slides)
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="475"| Mustafa Altun (ITU), Ceylan Morgul (ITU), and Onur Tunali (ITU) - Lorena Anghel (INPG) and Mehdi Tahoori (KIT)
|- valign="top"
|'''presented at''':
| width="475"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 2016.
|- valign="top"
|'''people reached''':
|Over 1000 attendees both from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]
|}

==Invited Talks ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays / Keynote Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.iaria.org/conferences2019/CENICS19.html The Twelfth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS'19)], Nice, France, 27-31 October 2019.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/8d/Altun_CENICS-2019.pptx]]

 [[Media:Altun_CENICS-2019.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Future and Emerging Computing Paradigms in Electronics / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://icecs2017.org/ 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)], Batumi, Georgia, 5-8 December 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/ff/Altun_ICECS-2017.pptx]]

 [[Media:Altun_ICECS-2017.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP / Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://sintesilogica.di.unimi.it/ National Workshop on Logic Synthesis (Organized)], Pisa, Italy, 5 July 2016
|- valign="top"
| '''people reached''':
|Over 50 attendees mostly from academia.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="476"| EU H2020 Success Story / Invited Talk
|- valign="top"
| width="1" | '''presenter(s)''':
| width="476"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="476"| [http://msca-association.teamwork.fr/index.php H2020 MSCA 2016 Istanbul Training & Info Event], Istanbul, Turkey, 13 June 2016
|- valign="top"
| '''people reached''':
| width="476"|Over 200 attendees from universities and research institutes (open to general public).
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Altun_MCSA_Info_Day-2016.pptx]]

 [[Media:Altun_MCSA_Info_Day-2016.pptx | Slides]]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/1/12/H2020_MCSA_Info_Day_Program_2016.pdf]]

 [[Media:H2020_MCSA_Info_Day_Program_2016.pdf | Program]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Circuit Design and Optimization of Nano-Crossbar Arrays / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://nanotr.org/en/ 12th Nanoscience and Nanotechnology Conference (NanoTR-12)], Kocaeli, Turkey, 3-5 June 2016.
|- valign="top"
| '''people reached''':
|Over 500 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/3/37/Altun_NanoTR12-2016.pptx]]

 [[Media:Altun_NanoTR12-2016.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Implementation of a Switching Nano-Crossbar Computer / Plenary Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.wseas.org/cms.action?id=11327 16th International Conference on APPLIED COMPUTER SCIENCE (ACS '16)], Istanbul, Turkey, 15-17 April 2016.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b2/Altun_ACT-2016.pptx]]

 [[Media:Altun_ACT-2016.pptx | Slides]]
|}

== Online Showcasing ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Video
|- valign="top"
| width="1" | '''prepared by''':
| width="550"| Mustafa Altun (ITU) and Ceylan Morgul (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://youtu.be/iwMSSvE1y8s YouTube].
|- valign="top"
|}
| align=center width="70" |

[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]
|}

== Magazine/Bulletin Columns ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Success Story from ITU - NANOxCOMP Project] / Article in a National Bulletin
|- valign="top"
| width="1" | '''author''':
| width="550"| Mustafa Altun (ITU)
|- valign=top
| '''appeared in''':
| [http://www.abmerkezi-arastirma.itu.edu.tr/yayinlarimiz/haber-bultenleri ITU Bulletin], September, Issue:5, 2017.
|- valign="top"
| '''people reached''':
| Publicly open, especially for university communities in Turkey.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2]]

 [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Bulletin]
|}

==Major Meetings of Project Personnel==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU) and Valentina Ciriani (UMIL).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 28 March 2019.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Valentina Ciriani (UMIL), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 20 March 2018.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/5/55/691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf]]

 [[Media:691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Midterm Review Meeting
|- valign="top"
| '''attendants''':
| width="550"| All project beneficiaries, the third country partner Mircea Stan, and almost all secondees attended.
|- valign="top"
| '''place''':
| width="550"| Lausanne, Switzerland, 27 March 2017.
|- valign="top"
| '''people reached''':
|Private meeting with the EU H2020 RISE Program representatives.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/4/45/1-691178-NANOxCOMP-MTM-agenda.pdf]]

 [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 15 March 2016.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

Publications and Presentations

2019-12-04T11:31:48Z

Altun: /* Papers on Fault Tolerance, Performance Modeling and Optimization */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2019-12-04T11:30:21Z

Altun: /* Papers on Fault Tolerance, Performance Modeling and Optimization */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]]

 [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |
[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

File:Yildiz Crossbar Analog Neural Network.pptx

2019-12-04T11:29:46Z

Altun:

File:Sirakoulis ICECS Memristor Networks SLIDES.pdf

2019-12-04T11:29:09Z

Altun:

Main Page

2019-11-17T10:00:36Z

Altun:

__NOTOC__

{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
|-
| colspan="2" style="background:#CEDFF2; text-align:center; padding:1px; border-bottom:1px #B8C7D9 solid;" |
<h2 style="margin:.5em; margin-top:.1em; border-bottom:1px; font-weight:bold;">
Welcome to the NANOxCOMP Project</h2>
|-
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;"  |

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer.

Project objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

[[Image:Research-nanoarray-1.png|center|none|800px|link=]]

<h2 id="mp-itn-h2" style="margin:0px; width:1010px; background:#F5F5F5; font-size:5%; font-weight:bold; border:0px solid #F5F5F5; text-align:left; color:#000; padding:0em 0em;"> </h2>

|}


{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"

| class="MainPageBG" style="width:50%; border:1px solid #B8C7D9; background:#8FBCCF; vertical-align:top; color:#000;" |
{| id="mp-left" style="width:100%; vertical-align:top; background:#F5F5F5;"

| style="padding:2px;" | <h2 id="mp-tafi-h2" style="margin:3px; background:#5F9EA0; font-size:125%; font-weight:bold; border:1px solid #4682B4; text-align:left; color:#000; padding:0.2em 0.4em;">Project details</h2>

{|
|- valign=top
| width="140" |'''title''':
| width="500"|Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
|- valign="top"
| width="140" |'''acronym''':
| width="500"|NANOxCOMP
|- valign="top"
| '''principal investigator / coordinator''':
| [http://www.ecc.itu.edu.tr/index.php?title=Mustafa_Altun Mustafa Altun], [http://www.ecc.itu.edu.tr/index.php?title=Main_Page ECC Group, Istanbul Technical University]
|- valign="top"
| '''partner(s)''':
| width="500"|
* Dr. Dan Alexandrescu, [http://www.iroctech.com/ IROC Techonogies], France 
* Prof. Lorena Anghel, [http://tima.imag.fr/tima/en/index.html TIMA Lab.], France (''partnership terminated'') 
* Prof. Valentina Ciriani, [http://alos.di.unimi.it/ ALOS Lab., University of Milan], Italy. 
* Prof. Csaba A. Moritz, [http://www.umass.edu/nanofabrics/ Nanoscale Computing Fabrics Lab., University of Massachusetts], USA 
* Prof. Kaushik Roy, [http://engineering.purdue.edu/NRL/index.html Nanoelectronics Research Lab., Purdue University], USA 
* Prof. Georgios Sirakoulis, [http://www.ee.duth.gr/en/ Department of Electrical and Computer Engineering, Democritus University of Thrace], Greece (''new partner'') 
* Prof. Mircea Stan, [http://hplp.ece.virginia.edu/home High-Performance Low-Power Lab., University of Virginia], USA 
* Prof. Mehdi B. Tahoori, [http://cdnc.itec.kit.edu/index.php Dependable Nano-Computing Group, Karlsruhe Institute of Technology], Germany

|- valign="top"
| '''funding agency & program''':
| width="500"| [http://ec.europa.eu/research/mariecurieactions/about-msca/actions/rise/index_en.htm European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)] [http://www.youtube.com/watch?v=dVeJFeKYrLs&feature=youtu.be RISE Video]
|- valign="top"
| '''budget''':
| 724.500 EURO
|- valign="top"
| '''duration''':
| 2015-2019
|}

{| style="margin-left: auto; margin-right: auto; border:1px solid #abd5f5; background:#CEDFE0; padding:0.2em 0.5em;"

|- valign=top
| |'''This project'''
* gathers globally leading research groups working on nanoelectronics and EDA;
* targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories; and
* contributes to the construction of emerging computers beyond CMOS by proposing nano-crossbar based computer architectures.
[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

[[Image:nanoxcomp_partners.png|center|none|450px|link=]]

|}

{|BORDER=0>
|-
<div><center>

'''PRESENTATIONS'''
<li style="display: inline-block;">


[[File:PPT.jpg|70px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]

</center></div>
|}

|}

----

<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.

| style="border:1px solid transparent;" |


| class="MainPageBG" style="width:50%; border:1px solid #BA55D3; background:#F8F8FF; vertical-align:top;"|
{| id="mp-right" style="width:100%; vertical-align:top; background:#F8F8FF;"
| style="padding:2px;" | <h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project activity news </h2>

* We present our work "''Nano-Crossbar based Computing: Lessons Learned and Future Directions''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''CMOS Implementation of Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''Analog Neural Network based on Memristor Crossbar Arrays''" in [http://www.eleco.org.tr/ ELECO 2019].

* We present our work "''Noise-induced Performance Enhancement of Variability-aware Memristor Networks''" in [http://www.ieee-icecs2019.org/ ICECS 2019].

* We give a keynote talk "''Computing with Nano-crossbar Arrays''" in [http://www.iaria.org/conferences2019/CENICS19.html CENICS 2019].

* We present our work "''Testability of Switching Lattices in the Cellular Fault Model''" in [http://dsd-seaa2019.csd.auth.gr/ DSD 2019].

* A new partner Prof. Georgios Sirakoulis from Democritus University of Thrace, Greece has joined our consortium. Welcome!

* We present our work "''Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model''" in [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ LATS 2019].

* We present our work "''Testability of Switching Lattices in the Stuck at Fault Model''" in [http://vlsi-soc.di.univr.it/ VLSI-Soc 2018].

* We present our work "''Integrated Synthesis Methodology for Crossbar Arrays''" in a leading conference on nanocircuits/nanoarchitectures [http://www.nanoarch.org IEEE/ACM-NANOARCH 2018].

* We showcase our project in a [http://youtu.be/iwMSSvE1y8s YouTube video].

* We present our work "''Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2018].

* We present our work "''Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions''" in [http://icecs2017.org/ IEEE-ICECS 2017].

* We publicly introduce our project in [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event].


* We present our work "''Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis''" in [http://dsd-seaa2017.ocg.at/dsd2017 DSD 2017].

* We present our work "''Spintronic Memristor based Offset Cancellation Technique for Sense Amplifiers''" in [http://smacd2017.unisa.it/ SMACD 2017].

* We successfully have our midterm review meeting in Lausanne, Switzerland on March 2017. For the agenda [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | click here]].

* We present our work "''Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2017].


* We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016].

* We present our project and our work on ''logic synthesis of switching nanoarrays'' in [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 DSD 2016].

* We give an invited talk "''EU H2020 Success Story''" in [http://msca-association.teamwork.fr/en/programme H2020 MSCA 2016 Istanbul Training & Info Event].

* We present our work "''Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays''" in [http://www.isvlsi.org/ IEEE-ISVLSI 2016].

* We organize [http://sintesilogica.di.unimi.it/ the National Workshop on Logic Synthesis, July 2016] with introducing our project and preliminary research results.

* We give an invited talk "''Circuit Design and Optimization of Nano-Crossbar Arrays''" in [http://www.nanotr12.org/ NanoTR-12].

* We give a plenary talk "''Implementation of a Switching Nano-Crossbar Computer''" in [http://www.wseas.org/cms.action?id=11327 ACS 2016].

* We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry.


[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

<!--
----
<div style="margin-left:0.8em;">If interested, please contact [[Mustafa_Altun|Mustafa]]:
* '''email:''' altunmus@itu.edu.tr
* '''office:''' EEF 3005 (coffee guaranteed)</div> -
<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.->
|}
|}

Main Page

2019-11-17T09:59:20Z

Altun:

__NOTOC__

{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
|-
| colspan="2" style="background:#CEDFF2; text-align:center; padding:1px; border-bottom:1px #B8C7D9 solid;" |
<h2 style="margin:.5em; margin-top:.1em; border-bottom:1px; font-weight:bold;">
Welcome to the NANOxCOMP Project</h2>
|-
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;"  |

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer.

Project objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

[[Image:Research-nanoarray-1.png|center|none|800px|link=]]

<h2 id="mp-itn-h2" style="margin:0px; width:1010px; background:#F5F5F5; font-size:5%; font-weight:bold; border:0px solid #F5F5F5; text-align:left; color:#000; padding:0em 0em;"> </h2>

|}


{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"

| class="MainPageBG" style="width:50%; border:1px solid #B8C7D9; background:#8FBCCF; vertical-align:top; color:#000;" |
{| id="mp-left" style="width:100%; vertical-align:top; background:#F5F5F5;"

| style="padding:2px;" | <h2 id="mp-tafi-h2" style="margin:3px; background:#5F9EA0; font-size:125%; font-weight:bold; border:1px solid #4682B4; text-align:left; color:#000; padding:0.2em 0.4em;">Project details</h2>

{|
|- valign=top
| width="140" |'''title''':
| width="500"|Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
|- valign="top"
| width="140" |'''acronym''':
| width="500"|NANOxCOMP
|- valign="top"
| '''principal investigator / coordinator''':
| [http://www.ecc.itu.edu.tr/index.php?title=Mustafa_Altun Mustafa Altun], [http://www.ecc.itu.edu.tr/index.php?title=Main_Page ECC Group, Istanbul Technical University]
|- valign="top"
| '''partner(s)''':
| width="500"|
* Dr. Dan Alexandrescu, [http://www.iroctech.com/ IROC Techonogies], France 
* Prof. Lorena Anghel, [http://tima.imag.fr/tima/en/index.html TIMA Lab.], France (''partnership terminated'') 
* Prof. Valentina Ciriani, [http://alos.di.unimi.it/ ALOS Lab., University of Milan], Italy. 
* Prof. Csaba A. Moritz, [http://www.umass.edu/nanofabrics/ Nanoscale Computing Fabrics Lab., University of Massachusetts], USA 
* Prof. Kaushik Roy, [http://engineering.purdue.edu/NRL/index.html Nanoelectronics Research Lab., Purdue University], USA 
* Prof. Georgios Sirakoulis, [http://www.ee.duth.gr/en/ Department of Electrical and Computer Engineering, Democritus University of Thrace], Greece (''new partner'') 
* Prof. Mircea Stan, [http://hplp.ece.virginia.edu/home High-Performance Low-Power Lab., University of Virginia], USA 
* Prof. Mehdi B. Tahoori, [http://cdnc.itec.kit.edu/index.php Dependable Nano-Computing Group, Karlsruhe Institute of Technology], Germany

|- valign="top"
| '''funding agency & program''':
| width="500"| [http://ec.europa.eu/research/mariecurieactions/about-msca/actions/rise/index_en.htm European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)] [http://www.youtube.com/watch?v=dVeJFeKYrLs&feature=youtu.be RISE Video]
|- valign="top"
| '''budget''':
| 724.500 EURO
|- valign="top"
| '''duration''':
| 2015-2019
|}

{| style="margin-left: auto; margin-right: auto; border:1px solid #abd5f5; background:#CEDFE0; padding:0.2em 0.5em;"

|- valign=top
| |'''This project'''
* gathers globally leading research groups working on nanoelectronics and EDA;
* targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories; and
* contributes to the construction of emerging computers beyond CMOS by proposing nano-crossbar based computer architectures.
[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

[[Image:nanoxcomp_partners.png|center|none|450px|link=]]

|}

{|BORDER=0>
|-
<div><center>

'''PRESENTATIONS'''
<li style="display: inline-block;">


[[File:PPT.jpg|70px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]

</center></div>
|}

|}

----

<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.

| style="border:1px solid transparent;" |


| class="MainPageBG" style="width:50%; border:1px solid #BA55D3; background:#F8F8FF; vertical-align:top;"|
{| id="mp-right" style="width:100%; vertical-align:top; background:#F8F8FF;"
| style="padding:2px;" | <h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project news</h2>

* We present our work "''Nano-Crossbar based Computing: Lessons Learned and Future Directions''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''CMOS Implementation of Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''Analog Neural Network based on Memristor Crossbar Arrays''" in [http://www.eleco.org.tr/ ELECO 2019].

* We present our work "''Noise-induced Performance Enhancement of Variability-aware Memristor Networks''" in [http://www.ieee-icecs2019.org/ ICECS 2019].

* We give a keynote talk "''Computing with Nano-crossbar Arrays''" in [http://www.iaria.org/conferences2019/CENICS19.html CENICS 2019].

* We present our work "''Testability of Switching Lattices in the Cellular Fault Model''" in [http://dsd-seaa2019.csd.auth.gr/ DSD 2019].

* A new partner Prof. Georgios Sirakoulis from Democritus University of Thrace, Greece has joined our consortium. Welcome!

* We present our work "''Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model''" in [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ LATS 2019].

* We present our work "''Testability of Switching Lattices in the Stuck at Fault Model''" in [http://vlsi-soc.di.univr.it/ VLSI-Soc 2018].

* We present our work "''Integrated Synthesis Methodology for Crossbar Arrays''" in a leading conference on nanocircuits/nanoarchitectures [http://www.nanoarch.org IEEE/ACM-NANOARCH 2018].

* We showcase our project in a [http://youtu.be/iwMSSvE1y8s YouTube video].

* We present our work "''Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2018].

* We present our work "''Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions''" in [http://icecs2017.org/ IEEE-ICECS 2017].

* We publicly introduce our project in [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event].


* We present our work "''Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis''" in [http://dsd-seaa2017.ocg.at/dsd2017 DSD 2017].

* We present our work "''Spintronic Memristor based Offset Cancellation Technique for Sense Amplifiers''" in [http://smacd2017.unisa.it/ SMACD 2017].

* We successfully have our midterm review meeting in Lausanne, Switzerland on March 2017. For the agenda [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | click here]].

* We present our work "''Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2017].


* We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016].

* We present our project and our work on ''logic synthesis of switching nanoarrays'' in [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 DSD 2016].

* We give an invited talk "''EU H2020 Success Story''" in [http://msca-association.teamwork.fr/en/programme H2020 MSCA 2016 Istanbul Training & Info Event].

* We present our work "''Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays''" in [http://www.isvlsi.org/ IEEE-ISVLSI 2016].

* We organize [http://sintesilogica.di.unimi.it/ the National Workshop on Logic Synthesis, July 2016] with introducing our project and preliminary research results.

* We give an invited talk "''Circuit Design and Optimization of Nano-Crossbar Arrays''" in [http://www.nanotr12.org/ NanoTR-12].

* We give a plenary talk "''Implementation of a Switching Nano-Crossbar Computer''" in [http://www.wseas.org/cms.action?id=11327 ACS 2016].

* We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry.


[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

<!--
----
<div style="margin-left:0.8em;">If interested, please contact [[Mustafa_Altun|Mustafa]]:
* '''email:''' altunmus@itu.edu.tr
* '''office:''' EEF 3005 (coffee guaranteed)</div> -
<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.->
|}
|}

Main Page

2019-11-17T09:57:00Z

Altun:

__NOTOC__

{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
|-
| colspan="2" style="background:#CEDFF2; text-align:center; padding:1px; border-bottom:1px #B8C7D9 solid;" |
<h2 style="margin:.5em; margin-top:.1em; border-bottom:1px; font-weight:bold;">
Welcome to the NANOxCOMP Project</h2>
|-
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;"  |

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer.

Project objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

[[Image:Research-nanoarray-1.png|center|none|800px|link=]]

<h2 id="mp-itn-h2" style="margin:0px; width:1010px; background:#F5F5F5; font-size:5%; font-weight:bold; border:0px solid #F5F5F5; text-align:left; color:#000; padding:0em 0em;"> </h2>

|}


{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"

| class="MainPageBG" style="width:50%; border:1px solid #B8C7D9; background:#8FBCCF; vertical-align:top; color:#000;" |
{| id="mp-left" style="width:100%; vertical-align:top; background:#F5F5F5;"

| style="padding:2px;" | <h2 id="mp-tafi-h2" style="margin:3px; background:#5F9EA0; font-size:125%; font-weight:bold; border:1px solid #4682B4; text-align:left; color:#000; padding:0.2em 0.4em;">Project details</h2>

{|
|- valign=top
| width="140" |'''title''':
| width="500"|Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
|- valign="top"
| width="140" |'''acronym''':
| width="500"|NANOxCOMP
|- valign="top"
| '''principal investigator / coordinator''':
| [http://www.ecc.itu.edu.tr/index.php?title=Mustafa_Altun Mustafa Altun], [http://www.ecc.itu.edu.tr/index.php?title=Main_Page ECC Group, Istanbul Technical University]
|- valign="top"
| '''partner(s)''':
| width="500"|
* Dr. Dan Alexandrescu, [http://www.iroctech.com/ IROC Techonogies], France 
* Prof. Lorena Anghel, [http://tima.imag.fr/tima/en/index.html TIMA Lab.], France (''partnership terminated'') 
* Prof. Valentina Ciriani, [http://alos.di.unimi.it/ ALOS Lab., University of Milan], Italy. 
* Prof. Csaba A. Moritz, [http://www.umass.edu/nanofabrics/ Nanoscale Computing Fabrics Lab., University of Massachusetts], USA 
* Prof. Kaushik Roy, [http://engineering.purdue.edu/NRL/index.html Nanoelectronics Research Lab., Purdue University], USA 
* Prof. Georgios Sirakoulis, [http://www.ee.duth.gr/en/ Department of Electrical and Computer Engineering, Democritus University of Thrace], Greece (''new partner'') 
* Prof. Mircea Stan, [http://hplp.ece.virginia.edu/home High-Performance Low-Power Lab., University of Virginia], USA 
* Prof. Mehdi B. Tahoori, [http://cdnc.itec.kit.edu/index.php Dependable Nano-Computing Group, Karlsruhe Institute of Technology], Germany

|- valign="top"
| '''funding agency & program''':
| width="500"| [http://ec.europa.eu/research/mariecurieactions/about-msca/actions/rise/index_en.htm European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)] [http://www.youtube.com/watch?v=dVeJFeKYrLs&feature=youtu.be RISE Video]
|- valign="top"
| '''budget''':
| 724.500 EURO
|- valign="top"
| '''duration''':
| 2015-2019
|}

{| style="margin-left: auto; margin-right: auto; border:1px solid #abd5f5; background:#CEDFE0; padding:0.2em 0.5em;"

|- valign=top
| |'''This project'''
* gathers globally leading research groups working on nanoelectronics and EDA;
* targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories; and
* contributes to the construction of emerging computers beyond CMOS by proposing nano-crossbar based computer architectures.
[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

[[Image:nanoxcomp_partners.png|center|none|450px|link=]]

|}

{|BORDER=0>
|-
<div><center>

'''PRESENTATIONS'''
<li style="display: inline-block;">


[[File:PPT.jpg|70px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]

<li style="display: inline-block;"> SPACE

<li style="display: inline-block;">


[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]

</center></div>
|}

|}

----

<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.

| style="border:1px solid transparent;" |


| class="MainPageBG" style="width:50%; border:1px solid #BA55D3; background:#F8F8FF; vertical-align:top;"|
{| id="mp-right" style="width:100%; vertical-align:top; background:#F8F8FF;"
| style="padding:2px;" | <h2 id="mp-itn-h2" style="margin:3px; background:#BC8F8F; font-size:125%; font-weight:bold; border:1px solid #BA55D3; text-align:left; color:#000; padding:0.2em 0.4em;">Project news</h2>

* We present our work "''Nano-Crossbar based Computing: Lessons Learned and Future Directions''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''CMOS Implementation of Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2020].

* We present our work "''Analog Neural Network based on Memristor Crossbar Arrays''" in [http://www.eleco.org.tr/ ELECO 2019].

* We present our work "''Noise-induced Performance Enhancement of Variability-aware Memristor Networks''" in [http://www.ieee-icecs2019.org/ ICECS 2019].

* We give a keynote talk "''Computing with Nano-crossbar Arrays''" in [http://www.iaria.org/conferences2019/CENICS19.html CENICS 2019].

* We present our work "''Testability of Switching Lattices in the Cellular Fault Model''" in [http://dsd-seaa2019.csd.auth.gr/ DSD 2019].

* A new partner Prof. Georgios Sirakoulis from Democritus University of Thrace, Greece has joined our consortium. Welcome!

* We present our work "''Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2019].

* We present our work "''Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model''" in [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ LATS 2019].

* We present our work "''Testability of Switching Lattices in the Stuck at Fault Model''" in [http://vlsi-soc.di.univr.it/ VLSI-Soc 2018].

* We present our work "''Integrated Synthesis Methodology for Crossbar Arrays''" in a leading conference on nanocircuits/nanoarchitectures [http://www.nanoarch.org IEEE/ACM-NANOARCH 2018].

* We showcase our project in a [http://youtu.be/iwMSSvE1y8s YouTube video].

* We present our work "''Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2018].

* We present our work "''Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions''" in [http://icecs2017.org/ IEEE-ICECS 2017].

* We publicly introduce our project in [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event].

* Our two papers in the area of ''fault tolerance for nano-crossbar arrays'' are accepted in journals [http://csur.acm.org/ CSUR] and [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 TETC] having impact factors of 6,8 and 3,8. This endorses our leading expertise in this area.

* We present our work "''Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis''" in [http://dsd-seaa2017.ocg.at/dsd2017 DSD 2017].

* We present our work "''Spintronic Memristor based Offset Cancellation Technique for Sense Amplifiers''" in [http://smacd2017.unisa.it/ SMACD 2017].

* We successfully have our midterm review meeting in Lausanne, Switzerland on March 2017. For the agenda [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | click here]].

* We present our work "''Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance''" in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2017].

* Our paper is accepted in a leading journal in design automation [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE TCAD].

* We present our work "''Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions''" in [http://ati.ttu.ee/vlsi-soc2016/ VLSI-Soc 2016].

* We present our project and our work on ''logic synthesis of switching nanoarrays'' in [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 DSD 2016].

* We give an invited talk "''EU H2020 Success Story''" in [http://msca-association.teamwork.fr/en/programme H2020 MSCA 2016 Istanbul Training & Info Event].

* We present our work "''Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays''" in [http://www.isvlsi.org/ IEEE-ISVLSI 2016].

* We organize [http://sintesilogica.di.unimi.it/ the National Workshop on Logic Synthesis, July 2016] with introducing our project and preliminary research results.

* We give an invited talk "''Circuit Design and Optimization of Nano-Crossbar Arrays''" in [http://www.nanotr12.org/ NanoTR-12].

* We give a plenary talk "''Implementation of a Switching Nano-Crossbar Computer''" in [http://www.wseas.org/cms.action?id=11327 ACS 2016].

* We present and exhibit our ''EU H2020 project NANOxCOMP'' in a premier conference on electronic design automation [http://www.date-conference.com/ DATE 2016] with over 1000 attendees from academia and industry.

* We publish a book chapter "''Computing with Emerging Nanotechnologies''" in a book [http://link.springer.com/book/10.1007/978-3-319-25340-4 "Low-Dimensional and Nanostructured Materials and Devices"].

[[Image:nanoxcomp_logo.png|center|none|300px|link=]]

<!--
----
<div style="margin-left:0.8em;">If interested, please contact [[Mustafa_Altun|Mustafa]]:
* '''email:''' altunmus@itu.edu.tr
* '''office:''' EEF 3005 (coffee guaranteed)</div> -
<div style="margin-left:0.8em;"> This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.->
|}
|}

Publications and Presentations

2019-11-15T15:25:46Z

Altun: /* Papers on Fault Tolerance, Performance Modeling and Optimization */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=]]
 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

File:Sirakoulis ICECS Memristor Networks.pdf

2019-11-15T15:24:11Z

Altun:

Publications and Presentations

2019-11-15T15:23:29Z

Altun: /* Papers on Fault Tolerance, Performance Modeling and Optimization */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=]]
 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2019-11-15T15:22:29Z

Altun: /* Papers on Fault Tolerance, Performance Modeling and Optimization */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]]
|- valign="top"
| '''authors''':
| width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rodriguez, and Montserrat Nafria
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Sirakoulis_ICECS_Memristor_Networks.pdf]]
 
[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=]]
 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2019-11-15T15:11:38Z

Altun: /* Papers on Fault Tolerance, Performance Modeling and Optimization */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=]]
 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2019-11-15T15:11:00Z

Altun: /* Papers on Fault Tolerance, Performance Modeling and Optimization */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=]]
 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

File:Yildiz Crossbar Analog Neural Network.pdf

2019-11-15T15:09:46Z

Altun:

Publications and Presentations

2019-11-15T15:08:42Z

Altun: /* Papers on Fault Tolerance, Performance Modeling and Optimization */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6f/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=]]
 Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2019-11-15T15:07:32Z

Altun: /* Papers on Fault Tolerance, Performance Modeling and Optimization */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6f/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2019-11-15T15:02:46Z

Altun: /* Papers on Fault Tolerance, Performance Modeling and Optimization */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2019.
|}

| align=center width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6f/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]

| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 
Slides

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

Publications and Presentations

2019-11-15T15:00:01Z

Altun: /* Papers on Fault Tolerance, Performance Modeling and Optimization */

All materials are subject to copyrights.
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Comprehensive Project Papers==
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
|- valign="top"
| '''authors''':
| Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
| '''presented at''':
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
|- valign="top"
| '''authors''':
| width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]
 
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

== Papers on Logic Synthesis ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''accepted in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
|- valign="top"
| '''authors''':
| Levent Aksoy and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]
 
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]
 
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]
 
[[Media:MICPRO2.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018.

|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]
 
[[Media:MICPRO1.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]
 
[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign=top
| '''presented at''':
| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]
 
[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa
|- valign=top
| '''presented at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]
 
[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul and Mustafa Altun
|- valign=top
| '''appeared in''':
| width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016.
|- valign="top"
| '''presented at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]
 
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
|}

== Papers on Fault Tolerance, Performance Modeling and Optimization ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays
Hacer]]
|- valign="top
| '''authors''':
| Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan
|- valign="top"
| '''presented at''':
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2019.
|}

| align=center width="70" |


[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6f/Yildiz_Crossbar_Analog_Neural_Network.pdf]]
 
[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]]

| align="center" width="70" |


[[File:PPT.jpg|60px|link=]]

 
Slides
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]
 
[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]]

| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]]
|- valign="top"
| '''authors''':
| width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu

|- valign="top"
| '''presented at''':
| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]
 
[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]]
|- valign="top"
| '''authors''':
| Anna Bernasconi, Valentina Ciriani, and Luca Frontini
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]
 
[[Media:Testability of Switching Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]

 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
|- valign="top"
| '''authors''':
| Onur Tunali, Ceylan Morgul, and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]
 
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Furkan Peker and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]
 
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]
 
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]
 
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''accepted in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]
 
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Onur Tunali and Mustafa Altun
|- valign="top"
| '''appeared in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
|- valign="top"
| '''authors''':
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
|- valign=top
| '''presented at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]
 
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

== Papers on Synthesis Methodology ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
|- valign="top"
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]
 
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

== Papers on Emerging Crossbar Memories ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
|- valign="top"
| '''authors''':
| width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz
|- valign=top
| '''appeared in''':
| width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]
 
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]]
|- valign="top"
| '''authors''':
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|}

| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]
 
[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

== Papers on Technology Development ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
|- valign="top"
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]
 
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

File:Nanoxcomp partners.png

2019-10-23T12:51:41Z

Altun:

Activities

2019-10-23T12:47:34Z

Altun: /* Invited Talks */

==Presentations of Published Papers==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Cellular Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Fault Mitigation of Switching Lattices under the Stuck-At Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|- valign="top"
| '''people reached''':
|Over 100 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Levent Aksoy (ITU), Serzat Safaltin (ITU), Mustafa Altun (ITU), and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Serzat Safaltin (ITU), Mustafa Altun (ITU), Valentina Ciriani (UMIL), and Levent Aksoy (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Stuck at Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|- valign="top"
| '''people reached''':
|Over 400 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]
 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Integrated Synthesis Methodology for Crossbar Arrays / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Ioana Vatajelu (INPG) and Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|- valign="top"
| '''people reached''':
|Over 300 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis and Defect Tolerance for Memristive Crossbar Array / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi, Valentina Ciriani (UMIL), and Gabriella Trucco (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mesut Atasoyu (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Mustafa Altun (ITU) – Kaushik Roy (PURDUE), Mircea Stan (UVA), Lorena Anghel (INPG), and Mehdi Tahoori (KIT)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Lausanne, Switzerland, 27-31 March 2017.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.
|}
| align=center width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://ati.ttu.ee/vlsi-soc2016/ IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, ESTONIA, 26-28 September 2016
|- valign="top"
| '''people reached''':
| Over 200 attendees mostly from academia.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis and Performance Optimization of a Switching Nano-crossbar Computer / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis for Switching Lattices by Decomposition with P-Circuits / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays / Poster
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Ceylan Morgul (ITU), Furkan Peker (ITU), and Mustafa Altun (ITU) - Mircea Stan (UVA)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, Pennsylvania, USA, 11-13 July 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

==Demonstrations and Exhibitions==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="402"| Journey of Computation and Nanocomputers / Demonstration and Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="402"| Tuba Ayhan (ITU), Mustafa Altun (ITU), Ceylan Morgul (ITU), Ensar Vahapoglu (ITU), Ismail Cevik (ITU), and Lida Kouhalvandi (ITU)
|- valign=top
| '''presented at''':
| width="402" | [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event]. Istanbul, Turkey 2017.
|- valign="top"
| '''people reached''':
| width="402" | Over 1000 attendees, mostly elementary and high school students, and general public.
|}
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/6/63/Altu_EU_NIGHT_Event-2017.pptx]]

 [[Media:Altu_EU_NIGHT_Event-2017.pptx | Slides-1]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fb/Ayhan_eu_night_hesaplama.pptx]]

 [[Media:ayhan_eu_night_hesaplama.pptx | Slides-2 ]]
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/81/Eu_night_poster.pdf]]

 [[Media:eu_night_poster.pdf | Poster]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="475"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Exhibition (Posters, Fliers and Slides)
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="475"| Mustafa Altun (ITU), Ceylan Morgul (ITU), and Onur Tunali (ITU) - Lorena Anghel (INPG) and Mehdi Tahoori (KIT)
|- valign="top"
|'''presented at''':
| width="475"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 2016.
|- valign="top"
|'''people reached''':
|Over 1000 attendees both from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]
|}

==Invited Talks ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays / Keynote Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.iaria.org/conferences2019/CENICS19.html The Twelfth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS'19)], Nice, France, 27-31 October 2019.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/8d/Altun_CENICS-2019.pptx]]

 [[Media:Altun_CENICS-2019.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Future and Emerging Computing Paradigms in Electronics / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://icecs2017.org/ 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)], Batumi, Georgia, 5-8 December 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/ff/Altun_ICECS-2017.pptx]]

 [[Media:Altun_ICECS-2017.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP / Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://sintesilogica.di.unimi.it/ National Workshop on Logic Synthesis (Organized)], Pisa, Italy, 5 July 2016
|- valign="top"
| '''people reached''':
|Over 50 attendees mostly from academia.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="476"| EU H2020 Success Story / Invited Talk
|- valign="top"
| width="1" | '''presenter(s)''':
| width="476"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="476"| [http://msca-association.teamwork.fr/index.php H2020 MSCA 2016 Istanbul Training & Info Event], Istanbul, Turkey, 13 June 2016
|- valign="top"
| '''people reached''':
| width="476"|Over 200 attendees from universities and research institutes (open to general public).
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Altun_MCSA_Info_Day-2016.pptx]]

 [[Media:Altun_MCSA_Info_Day-2016.pptx | Slides]]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/1/12/H2020_MCSA_Info_Day_Program_2016.pdf]]

 [[Media:H2020_MCSA_Info_Day_Program_2016.pdf | Program]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Circuit Design and Optimization of Nano-Crossbar Arrays / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://nanotr.org/en/ 12th Nanoscience and Nanotechnology Conference (NanoTR-12)], Kocaeli, Turkey, 3-5 June 2016.
|- valign="top"
| '''people reached''':
|Over 500 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/3/37/Altun_NanoTR12-2016.pptx]]

 [[Media:Altun_NanoTR12-2016.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Implementation of a Switching Nano-Crossbar Computer / Plenary Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.wseas.org/cms.action?id=11327 16th International Conference on APPLIED COMPUTER SCIENCE (ACS '16)], Istanbul, Turkey, 15-17 April 2016.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b2/Altun_ACT-2016.pptx]]

 [[Media:Altun_ACT-2016.pptx | Slides]]
|}

== Online Showcasing ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Video
|- valign="top"
| width="1" | '''prepared by''':
| width="550"| Mustafa Altun (ITU) and Ceylan Morgul (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://youtu.be/iwMSSvE1y8s YouTube].
|- valign="top"
|}
| align=center width="70" |

[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]
|}

== Magazine/Bulletin Columns ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Success Story from ITU - NANOxCOMP Project] / Article in a National Bulletin
|- valign="top"
| width="1" | '''author''':
| width="550"| Mustafa Altun (ITU)
|- valign=top
| '''appeared in''':
| [http://www.abmerkezi-arastirma.itu.edu.tr/yayinlarimiz/haber-bultenleri ITU Bulletin], September, Issue:5, 2017.
|- valign="top"
| '''people reached''':
| Publicly open, especially for university communities in Turkey.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2]]

 [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Bulletin]
|}

==Major Meetings of Project Personnel==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU) and Valentina Ciriani (UMIL).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 28 March 2019.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Valentina Ciriani (UMIL), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 20 March 2018.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/5/55/691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf]]

 [[Media:691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Midterm Review Meeting
|- valign="top"
| '''attendants''':
| width="550"| All project beneficiaries, the third country partner Mircea Stan, and almost all secondees attended.
|- valign="top"
| '''place''':
| width="550"| Lausanne, Switzerland, 27 March 2017.
|- valign="top"
| '''people reached''':
|Private meeting with the EU H2020 RISE Program representatives.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/4/45/1-691178-NANOxCOMP-MTM-agenda.pdf]]

 [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 15 March 2016.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

Activities

2019-10-23T12:47:22Z

Altun: /* Invited Talks */

==Presentations of Published Papers==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Cellular Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Fault Mitigation of Switching Lattices under the Stuck-At Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|- valign="top"
| '''people reached''':
|Over 100 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Levent Aksoy (ITU), Serzat Safaltin (ITU), Mustafa Altun (ITU), and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Serzat Safaltin (ITU), Mustafa Altun (ITU), Valentina Ciriani (UMIL), and Levent Aksoy (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Stuck at Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|- valign="top"
| '''people reached''':
|Over 400 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]
 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Integrated Synthesis Methodology for Crossbar Arrays / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Ioana Vatajelu (INPG) and Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|- valign="top"
| '''people reached''':
|Over 300 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis and Defect Tolerance for Memristive Crossbar Array / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi, Valentina Ciriani (UMIL), and Gabriella Trucco (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mesut Atasoyu (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Mustafa Altun (ITU) – Kaushik Roy (PURDUE), Mircea Stan (UVA), Lorena Anghel (INPG), and Mehdi Tahoori (KIT)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Lausanne, Switzerland, 27-31 March 2017.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.
|}
| align=center width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://ati.ttu.ee/vlsi-soc2016/ IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, ESTONIA, 26-28 September 2016
|- valign="top"
| '''people reached''':
| Over 200 attendees mostly from academia.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis and Performance Optimization of a Switching Nano-crossbar Computer / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis for Switching Lattices by Decomposition with P-Circuits / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays / Poster
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Ceylan Morgul (ITU), Furkan Peker (ITU), and Mustafa Altun (ITU) - Mircea Stan (UVA)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, Pennsylvania, USA, 11-13 July 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

==Demonstrations and Exhibitions==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="402"| Journey of Computation and Nanocomputers / Demonstration and Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="402"| Tuba Ayhan (ITU), Mustafa Altun (ITU), Ceylan Morgul (ITU), Ensar Vahapoglu (ITU), Ismail Cevik (ITU), and Lida Kouhalvandi (ITU)
|- valign=top
| '''presented at''':
| width="402" | [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event]. Istanbul, Turkey 2017.
|- valign="top"
| '''people reached''':
| width="402" | Over 1000 attendees, mostly elementary and high school students, and general public.
|}
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/6/63/Altu_EU_NIGHT_Event-2017.pptx]]

 [[Media:Altu_EU_NIGHT_Event-2017.pptx | Slides-1]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fb/Ayhan_eu_night_hesaplama.pptx]]

 [[Media:ayhan_eu_night_hesaplama.pptx | Slides-2 ]]
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/81/Eu_night_poster.pdf]]

 [[Media:eu_night_poster.pdf | Poster]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="475"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Exhibition (Posters, Fliers and Slides)
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="475"| Mustafa Altun (ITU), Ceylan Morgul (ITU), and Onur Tunali (ITU) - Lorena Anghel (INPG) and Mehdi Tahoori (KIT)
|- valign="top"
|'''presented at''':
| width="475"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 2016.
|- valign="top"
|'''people reached''':
|Over 1000 attendees both from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]
|}

==Invited Talks ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays/ Keynote Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.iaria.org/conferences2019/CENICS19.html The Twelfth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS'19)], Nice, France, 27-31 October 2019.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/8d/Altun_CENICS-2019.pptx]]

 [[Media:Altun_CENICS-2019.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Future and Emerging Computing Paradigms in Electronics / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://icecs2017.org/ 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)], Batumi, Georgia, 5-8 December 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/ff/Altun_ICECS-2017.pptx]]

 [[Media:Altun_ICECS-2017.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP / Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://sintesilogica.di.unimi.it/ National Workshop on Logic Synthesis (Organized)], Pisa, Italy, 5 July 2016
|- valign="top"
| '''people reached''':
|Over 50 attendees mostly from academia.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="476"| EU H2020 Success Story / Invited Talk
|- valign="top"
| width="1" | '''presenter(s)''':
| width="476"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="476"| [http://msca-association.teamwork.fr/index.php H2020 MSCA 2016 Istanbul Training & Info Event], Istanbul, Turkey, 13 June 2016
|- valign="top"
| '''people reached''':
| width="476"|Over 200 attendees from universities and research institutes (open to general public).
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Altun_MCSA_Info_Day-2016.pptx]]

 [[Media:Altun_MCSA_Info_Day-2016.pptx | Slides]]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/1/12/H2020_MCSA_Info_Day_Program_2016.pdf]]

 [[Media:H2020_MCSA_Info_Day_Program_2016.pdf | Program]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Circuit Design and Optimization of Nano-Crossbar Arrays / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://nanotr.org/en/ 12th Nanoscience and Nanotechnology Conference (NanoTR-12)], Kocaeli, Turkey, 3-5 June 2016.
|- valign="top"
| '''people reached''':
|Over 500 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/3/37/Altun_NanoTR12-2016.pptx]]

 [[Media:Altun_NanoTR12-2016.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Implementation of a Switching Nano-Crossbar Computer / Plenary Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.wseas.org/cms.action?id=11327 16th International Conference on APPLIED COMPUTER SCIENCE (ACS '16)], Istanbul, Turkey, 15-17 April 2016.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b2/Altun_ACT-2016.pptx]]

 [[Media:Altun_ACT-2016.pptx | Slides]]
|}

== Online Showcasing ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Video
|- valign="top"
| width="1" | '''prepared by''':
| width="550"| Mustafa Altun (ITU) and Ceylan Morgul (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://youtu.be/iwMSSvE1y8s YouTube].
|- valign="top"
|}
| align=center width="70" |

[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]
|}

== Magazine/Bulletin Columns ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Success Story from ITU - NANOxCOMP Project] / Article in a National Bulletin
|- valign="top"
| width="1" | '''author''':
| width="550"| Mustafa Altun (ITU)
|- valign=top
| '''appeared in''':
| [http://www.abmerkezi-arastirma.itu.edu.tr/yayinlarimiz/haber-bultenleri ITU Bulletin], September, Issue:5, 2017.
|- valign="top"
| '''people reached''':
| Publicly open, especially for university communities in Turkey.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2]]

 [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Bulletin]
|}

==Major Meetings of Project Personnel==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU) and Valentina Ciriani (UMIL).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 28 March 2019.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Valentina Ciriani (UMIL), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 20 March 2018.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/5/55/691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf]]

 [[Media:691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Midterm Review Meeting
|- valign="top"
| '''attendants''':
| width="550"| All project beneficiaries, the third country partner Mircea Stan, and almost all secondees attended.
|- valign="top"
| '''place''':
| width="550"| Lausanne, Switzerland, 27 March 2017.
|- valign="top"
| '''people reached''':
|Private meeting with the EU H2020 RISE Program representatives.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/4/45/1-691178-NANOxCOMP-MTM-agenda.pdf]]

 [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 15 March 2016.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

File:Altun CENICS-2019.pptx

2019-10-23T12:46:43Z

Altun:

Activities

2019-10-23T12:46:29Z

Altun: /* Invited Talks */

==Presentations of Published Papers==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Cellular Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]]

 [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Fault Mitigation of Switching Lattices under the Stuck-At Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019.
|- valign="top"
| '''people reached''':
|Over 100 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Levent Aksoy (ITU), Serzat Safaltin (ITU), Mustafa Altun (ITU), and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Serzat Safaltin (ITU), Mustafa Altun (ITU), Valentina Ciriani (UMIL), and Levent Aksoy (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
|- valign="top"
| '''people reached''':
|Over 1600 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]

 [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Testability of Switching Lattices in the Stuck at Fault Model / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) and Valentina Ciriani (UMIL)
|- valign=top
| '''presented at''':
| [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018.
|- valign="top"
| '''people reached''':
|Over 400 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]]
 [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Integrated Synthesis Methodology for Crossbar Arrays / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Ioana Vatajelu (INPG) and Lorena Anghel (INPG)
|- valign=top
| '''presented at''':
| width="550"| [http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
|- valign="top"
| '''people reached''':
|Over 300 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis and Defect Tolerance for Memristive Crossbar Array / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]

 [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mustafa Altun (ITU) and Onur Tunali (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]

 [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Anna Bernasconi, Valentina Ciriani (UMIL), and Gabriella Trucco (UMIL)
|- valign=top
| '''presented at''':
| [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"

|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| Mesut Atasoyu (ITU)
|- valign=top
| '''presented at''':
| width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees, mostly researchers, both from academia and industry.

|}
| align="center" width="70" |


[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]

 [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Mustafa Altun (ITU) – Kaushik Roy (PURDUE), Mircea Stan (UVA), Lorena Anghel (INPG), and Mehdi Tahoori (KIT)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Lausanne, Switzerland, 27-31 March 2017.
|- valign="top"
| '''people reached''':
|Over 1000 attendees, mostly researchers, both from academia and industry.
|}
| align=center width="70" |


[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://ati.ttu.ee/vlsi-soc2016/ IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, ESTONIA, 26-28 September 2016
|- valign="top"
| '''people reached''':
| Over 200 attendees mostly from academia.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Synthesis and Performance Optimization of a Switching Nano-crossbar Computer / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]

 [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Logic Synthesis for Switching Lattices by Decomposition with P-Circuits / Presentation
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php?p=DSD2016 The Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 31 August-2 September 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]]

 [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays / Poster
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Ceylan Morgul (ITU), Furkan Peker (ITU), and Mustafa Altun (ITU) - Mircea Stan (UVA)
|- valign="top"
| '''presented at''':
| width="550"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, Pennsylvania, USA, 11-13 July 2016
|- valign="top"
| '''people reached''':
|Over 300 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
|}

==Demonstrations and Exhibitions==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="402"| Journey of Computation and Nanocomputers / Demonstration and Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="402"| Tuba Ayhan (ITU), Mustafa Altun (ITU), Ceylan Morgul (ITU), Ensar Vahapoglu (ITU), Ismail Cevik (ITU), and Lida Kouhalvandi (ITU)
|- valign=top
| '''presented at''':
| width="402" | [http://www.english.sci-all.com/ Science Unites All (SCI-ALL) 2017] - [http://ec.europa.eu/research/mariecurieactions/about/researchers-night_en European Researchers' Night Event]. Istanbul, Turkey 2017.
|- valign="top"
| '''people reached''':
| width="402" | Over 1000 attendees, mostly elementary and high school students, and general public.
|}
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/6/63/Altu_EU_NIGHT_Event-2017.pptx]]

 [[Media:Altu_EU_NIGHT_Event-2017.pptx | Slides-1]]
| align="center" width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fb/Ayhan_eu_night_hesaplama.pptx]]

 [[Media:ayhan_eu_night_hesaplama.pptx | Slides-2 ]]
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/81/Eu_night_poster.pdf]]

 [[Media:eu_night_poster.pdf | Poster]]

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="475"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Exhibition (Posters, Fliers and Slides)
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="475"| Mustafa Altun (ITU), Ceylan Morgul (ITU), and Onur Tunali (ITU) - Lorena Anghel (INPG) and Mehdi Tahoori (KIT)
|- valign="top"
|'''presented at''':
| width="475"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 2016.
|- valign="top"
|'''people reached''':
|Over 1000 attendees both from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx]]

 [http://www.ecc.itu.edu.tr/images/5/57/NANOxCOMP_DATE16_slides_2016.pptx Slides]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.ecc.itu.edu.tr/images/2/29/NANOxCOMP_DATE16_poster_2016.pdf]]

 [[Media:NANOxCOMP_DATE16_poster_2016.pdf | Poster]]
|}

==Invited Talks ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Computing with Nano-Crossbar Arrays/ Keynote Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.iaria.org/conferences2019/CENICS19.html The Twelfth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS'19)], Nice, France, 27-31 October 2019.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b2/Altun_CENICS-2019.pptx]]

 [[Media:Altun_CENICS-2019.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Future and Emerging Computing Paradigms in Electronics / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://icecs2017.org/ 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)], Batumi, Georgia, 5-8 December 2017.
|- valign="top"
| '''people reached''':
|Over 200 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/f/ff/Altun_ICECS-2017.pptx]]

 [[Media:Altun_ICECS-2017.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP / Presentation in a National Event
|- valign="top"
| width="1" | '''presenter(s) - attendant(s)''':
| width="550"| Luca Frontini (UMIL) – Valentina Ciriani (UMIL) and Valentino Liberali (UMIL)
|- valign="top"
| '''presented at''':
| width="550"| [http://sintesilogica.di.unimi.it/ National Workshop on Logic Synthesis (Organized)], Pisa, Italy, 5 July 2016
|- valign="top"
| '''people reached''':
|Over 50 attendees mostly from academia.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="476"| EU H2020 Success Story / Invited Talk
|- valign="top"
| width="1" | '''presenter(s)''':
| width="476"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="476"| [http://msca-association.teamwork.fr/index.php H2020 MSCA 2016 Istanbul Training & Info Event], Istanbul, Turkey, 13 June 2016
|- valign="top"
| '''people reached''':
| width="476"|Over 200 attendees from universities and research institutes (open to general public).
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Altun_MCSA_Info_Day-2016.pptx]]

 [[Media:Altun_MCSA_Info_Day-2016.pptx | Slides]]
| align="center" width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/1/12/H2020_MCSA_Info_Day_Program_2016.pdf]]

 [[Media:H2020_MCSA_Info_Day_Program_2016.pdf | Program]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Circuit Design and Optimization of Nano-Crossbar Arrays / Invited Talk
|- valign="top"
| '''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://nanotr.org/en/ 12th Nanoscience and Nanotechnology Conference (NanoTR-12)], Kocaeli, Turkey, 3-5 June 2016.
|- valign="top"
| '''people reached''':
|Over 500 attendees from academia and industry in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/3/37/Altun_NanoTR12-2016.pptx]]

 [[Media:Altun_NanoTR12-2016.pptx | Slides]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| Implementation of a Switching Nano-Crossbar Computer / Plenary Talk
|- valign="top"
|'''presenter(s)''':
| width="550"| Mustafa Altun (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://www.wseas.org/cms.action?id=11327 16th International Conference on APPLIED COMPUTER SCIENCE (ACS '16)], Istanbul, Turkey, 15-17 April 2016.
|- valign="top"
|'''people reached''':
|Over 100 attendees mostly from academia in the conference.
|}
| align=center width="70" |

[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b2/Altun_ACT-2016.pptx]]

 [[Media:Altun_ACT-2016.pptx | Slides]]
|}

== Online Showcasing ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| NANOxCOMP - Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer / Video
|- valign="top"
| width="1" | '''prepared by''':
| width="550"| Mustafa Altun (ITU) and Ceylan Morgul (ITU)
|- valign="top"
|'''presented at''':
| width="550"| [http://youtu.be/iwMSSvE1y8s YouTube].
|- valign="top"
|}
| align=center width="70" |

[[File:VIDEO.png|70px|link=http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be]]

 [http://www.youtube.com/watch?v=iwMSSvE1y8s&feature=youtu.be Video]
|}

== Magazine/Bulletin Columns ==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''title / type''':
| width="550"| [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Success Story from ITU - NANOxCOMP Project] / Article in a National Bulletin
|- valign="top"
| width="1" | '''author''':
| width="550"| Mustafa Altun (ITU)
|- valign=top
| '''appeared in''':
| [http://www.abmerkezi-arastirma.itu.edu.tr/yayinlarimiz/haber-bultenleri ITU Bulletin], September, Issue:5, 2017.
|- valign="top"
| '''people reached''':
| Publicly open, especially for university communities in Turkey.
|}
| align="center" width="70" |

[[File:PDF.png|65px|link=http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2]]

 [http://www.abmerkezi-arastirma.itu.edu.tr/docs/librariesprovider81/haber-bultenleri/eyl%c3%bcl-ekim-2017-b%c3%bclteni.pdf?sfvrsn=2 Bulletin]
|}

==Major Meetings of Project Personnel==

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU) and Valentina Ciriani (UMIL).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 28 March 2019.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Valentina Ciriani (UMIL), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 20 March 2018.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/5/55/691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf]]

 [[Media:691178-NANOxCOMP-Meeting-Agenda-Dresden-2018.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Midterm Review Meeting
|- valign="top"
| '''attendants''':
| width="550"| All project beneficiaries, the third country partner Mircea Stan, and almost all secondees attended.
|- valign="top"
| '''place''':
| width="550"| Lausanne, Switzerland, 27 March 2017.
|- valign="top"
| '''people reached''':
|Private meeting with the EU H2020 RISE Program representatives.
|}
| align=center width="70" |

[[File:PDF.png|70px|link=http://www.nanoxcomp.itu.edu.tr/images/4/45/1-691178-NANOxCOMP-MTM-agenda.pdf]]

 [[Media:1-691178-NANOxCOMP-MTM-agenda.pdf | Agenda]]
|}

{| style="border:2px solid #abd5f5; background:#f1f5fc;"
|
{|
|- valign=top
| width="100" |'''subject''':
| width="550"| Annual Meeting of Project Beneficiaries
|- valign="top"
| '''attendants''':
| width="550"| Mustafa Altun (ITU), Lorena Anghel (INPG), and Mehdi Tahoori (KIT).
|- valign="top"
| '''place''':
| width="550"| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE) Conference], Dresden, Germany, 15 March 2016.
|- valign="top"
| '''people reached''':
|Private.
|}
| align=center width="70" |

|}